娄鑫，上海科技大学信息科学与技术学院长聘副教授（Tenured）、研究员、博士生导师。

娄鑫博士于2010年、2012年以及2016年毕业于浙江大学 (ZJU)、瑞典皇家理工学院 (KTH) 以及新加坡南洋理工大学 (NTU)，分别获得学士、硕士以及博士学位。博士毕业后，加入南洋理工大学VIRTUS集成电路设计中心担任研究科学家。他于2017年3月全职加入上海科技大学信息科学与技术学院，现为长聘副教授（Tenured）、研究员、博士生导师。娄鑫博士的研究兴趣为数字VLSI设计，特别是面向3D神经渲染、图像、视觉处理等应用的高性能数字芯片设计，目前已在相关领域国际知名期刊及会议 (IEEE TCAS-I, CICC, TPAMI, TIP, SIGGRAPH-Asia 等）上发表学术论文60余篇。娄鑫博士是IEEE高级会员，CCF集成电路设计专委，目前担任IEEE TCAS-II的副编辑 (Associate Editor), TCAS-I 客座编辑(Guest Editor) 以及IEEE CAS 技术委员会委员。

SI100B 《信息科技导论》（本科生）

EE218 《数字VLSI设计》（研究生）

EE291F《数字VLSI 设计流程》（研究生）

Journal:

[J30]L. Zhang, H. Li, X. Zhang and X. Lou*, “RAW Images-based Motion-assisted Object Detection Accelerator Using Deformable Parts Models Features on 1080p Videos”, in IEEE Transactions on Circuits and Systems I: Regular Papers, accepted.

[J29]J. Ding, Y. He, B. Yuan, Z. Yuan, P. Zhou, J. Yu and X. Lou*, “Ray Reordering for Hardware-Accelerated Neural Volume Rendering”, in IEEE Transactions on Circuits and Systems for Video Technology, accepted.

[J28] K. Long, C. Rao, X. Zhang, W. Ye and X. Lou*, “FPGA Accelerator for Human Activity Recognition Based on Radar”, in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 3, pp. 1441-1445, Mar. 2024, doi: 10.1109/TCSII.2023.3328422.

[J27] K. Long, C. Rao, Y. He, Z. Yuan, P. Zhou, J. Yu* and X. Lou*, “Analysis and Design of Precision-scalable Computation Array for Efficient Neural Radiance Field Rendering”, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 11, pp. 4260-4270, Nov. 2023, doi: 10.1109/TCSI.2023.3293534.

[J26] L. Zhang, C. Rao and X. Lou*, “Low-power Reconfigurable FIR Filter Design Based on Common Operation Sharing”, in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 8, pp. 3169-3173, Aug. 2023, doi: 10.1109/TCSII.2023.3256446.

[J25] C. Rao, Q. Wu, H. Wan, P. Zhou, J. Yu, Y. Zhang* and X. Lou*, “An Energy-efficient Accelerator for Medical Image Reconstruction from Implicit Neural Representation”, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 4, pp. 1625-1638, Apr. 2023, doi: 10.1109/TCSI.2022.3231863.

[J24]C. Rao, H. Yu, H. Wan, J. Zhou, Y. Zheng, M. Wu, Y. Ma, A. Chen, B. Yuan, P. Zhou, X. Lou*, and J. Yu*, “ICARUS: A Specialized Architecture for Neural Radiance Fields Rendering”, in ACM Transactions on Graphics, Volume 41, Issue 6, Nov. 2022 (SIGGRAPH-Asia 2022), doi: 10.1145/3550454.3555505.

[J23] X. Zheng, Z. Liao, Y. Wei, X. Zhang and X. Lou*, “Design of FRM-based Nonuniform Filter Bank with Reduced Effective Wordlength for Hearing Aids”, in IEEE Transactions on Biomedical Circuits and Systems, vol. 16, no. 6, pp. 1216-1227, Dec. 2022, doi: 10.1109/TBCAS.2022.3221359.

[J22] J. Geng, S. Wang, Q. Liu and X. Lou*, “A Time-Frequency Bins Selection Pipeline for Direction-of-Arrival Estimation Using a Single Acoustic Vector Sensor”, in IEEE Sensors Journal, vol. 22, no. 14, pp. 14306-14319, Jul. 2022, doi: 10.1109/JSEN.2022.3180157.

[J21] H. Wang, W. Zhou, X. Zhang and X. Lou*, “A Block PatchMatch-based Energy-resource Efficient Stereo Matching Processor on FPGA”, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 7, pp. 2893-2905, Jul. 2022, doi: 10.1109/TCSI.2022.3161266.

[J20] J. Geng, S. Wang, Q. Liu and X. Lou*, “Multi-Level Time-Frequency Bins Selection for Direction of Arrival Estimation Using a Single Acoustic Vector Sensor”, in IEEE/ACM Transactions on Audio, Speech, and Language Processing, vol. 30, pp. 1048-1060, 2022, doi: 10.1109/TASLP.2022.3155276.

[J19] Z. Liao, D. Jiang, X. Liu, A. Velten, Y. Ha and X. Lou*, “FPGA Accelerator for Real-Time Non-Line-of-Sight Imaging”, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 2, pp. 721-734, Feb. 2022, doi: 10.1109/TCSI.2021.3122309.

[J18] D. Jiang, X. Liu, J. Luo, Z. Liao, A. Velten and X. Lou*, “Ring and Radius Sampling Based Phasor Field Diffraction Algorithm for Non-Line-of-Sight Reconstruction”, in IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 44, no. 11, pp. 7841-7853, 1 Nov. 2022, doi: 10.1109/TPAMI.2021.3117962.

[J17] X. Zhang, L. Zhang and X. Lou*, “A Raw Image-based End-to-end Object Detection Accelerator using HOG Features”, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 1, pp. 322-333, Jan. 2022, doi: 10.1109/TCSI.2021.3098053.

[J16] T. Ma, Y. Wei and X. Lou, “Reconfigurable Nonuniform Filter Bank for Hearing Aid Systems”, in IEEE/ACM Transactions on Audio, Speech, and Language Processing, vol. 30, pp. 758-771, Dec. 2022, doi: 10.1109/TASLP.2021.3138713.

[J15] S. Gao, H. Wang and X. Lou*, “A Low-Complexity End-to-End Stereo Matching Pipeline from Raw Bayer Pattern Images to Disparity Maps”, in IEEE Access, vol. 9, pp. 47786-47794, 2021, doi: 10.1109/ACCESS.2021.3068497.

[J14] D. She, X. Lou and W. Ye, “RadarSpecAugment: A Simple Data Augmentation Method for Radar-based Human Activity Recognition”, in IEEE Sensors Letters, vol. 5, no. 4, pp. 1-4, April 2021, Art no. 7001004, doi: 10.1109/LSENS.2021.3061561.

[J13] W. Zhou, L. Zhang, S. Gao and X. Lou*, “Gradient-based Feature Extraction from Raw Bayer Pattern Images”, in IEEE Transactions on Image Processing, vol. 30, pp. 5122-5137, 2021, doi: 10.1109/TIP.2021.3067166.

[J12] J. Zhu, X. Lou and W. Ye, “Lightweight Deep Learning Model in Mobile-Edge Computing for Radar-Based Human Activity Recognition”, in IEEE Internet of Things Journal, vol. 8, no. 15, pp. 12350-12359, 1 Aug.1, 2021, doi: 10.1109/JIOT.2021.3063504.

[J11] G. Lai, X. Lou and W. Ye, “Radar-Based Human Activity Recognition with 1-D Dense Attention Network, in IEEE Geoscience and Remote Sensing Letters, vol. 19, pp. 1-5, 2022, Art no. 3502505, doi: 10.1109/LGRS.2020.3045176.

[J10] W. Zhou, S. Gao, L. Zhang and X. Lou*, “Histogram of Oriented Gradients Feature Extraction from Raw Bayer Pattern Images”, in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 5, pp. 946-950, May 2020, doi: 10.1109/TCSII.2020.2980557.

[J9] W. Chen, M. Huang, W. Ye and X. Lou*, “Cascaded Form Sparse FIR Filter Design”, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 5, pp. 1692-1703, May 2020, doi: 10.1109/TCSI.2020.2964568.

[J8] W. Chen, M. Huang and X. Lou*, “Design of Sparse FIR Filters with Reduced Effective Length”, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 4, pp. 1496-1506, April 2019, doi: 10.1109/TCSI.2018.2883965.

[J7] W. Ye, X. Lou* and Y. J. Yu, “Design of Low-Power Multiplierless Linear-Phase FIR Filters”, in IEEE Access, vol. 5, pp. 23466-23472, 2017, doi: 10.1109/ACCESS.2017.2740422.

[J6]X. Lou*, P. K. Meher, Y. J. Yu and W. B. Ye, “Novel Structure for Area-Efficient Implementation of FIR Filter”, in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 10, pp. 1212-1216, Oct. 2017, doi: 10.1109/TCSII.2016.2614727.

[J5] P. K. Meher, and X. Lou*, “Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for GF(2^m) Based on Irreducible All-One Polynomials”, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 2, pp. 399-408, Feb. 2017, doi: 10.1109/TCSI.2016.2614309.

[J4]X. Lou*, Y. J. Yu and P. K. Meher, “Lower Bound Analysis and Perturbation of Critical Path for Area-Time Efficient Multiple Constant Multiplications”, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 2, pp. 313-324, Feb. 2017, doi: 10.1109/TCAD.2016.2584181.

[J3]X. Lou*, Y. J. Yu and P. K. Meher, “Analysis and Optimization of Product-Accumulation Section for Efficient Implementation of FIR Filters”, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 10, pp. 1701-1713, Oct. 2016, doi: 10.1109/TCSI.2016.2587105.

[J2] X. Lou*, Y. J. Yu and P. K. Meher, “New Approach to the Reduction of Sign-extension Overhead for Efficient Implementation of Multiple Constant Multiplications”, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 11, pp. 2695-2705, Nov. 2015, doi: 10.1109/TCSI.2015.2476319.

[J1]X. Lou*, Y. J. Yu and P. K. Meher, “Fine-Grained Critical Path Analysis and Optimization for Area-Time Efficient Realization of Multiple Constant Multiplications”, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 3, pp. 863-872, March 2015, doi: 10.1109/TCSI.2014.2377412.

Conference:

[C40] W. Liu, X. Zheng, J. Yu and X. Lou*, “Content-Aware Radiance Fields: Aligning Model Complexity with Scene Intricacy Through Learned Bitwidth Quantization”, 2024 European Conference on Computer Vision (ECCV), 2024.

[C39] Y. Yang, Z. Yuan, Y. He, J. Li and X. Lou*, “A Novel Block-Wise Hash Encoding Engine for Neural Volume Rendering”, 2024 IEEE Interregional NEWCAS Conference (NEWCAS), Sherbrooke, Quebec, Canada, 2024.

[C38] H. Wan, L. Ma, A. Li, P. Zhou, J. Yu andX. Lou*, “ZeroTetris: A Spacial Features Similarity-based Sparse MLP Engine for Neural Volume Rendering,” in Proc., 2024 ACM/IEEE Design Automation Conference (DAC), 2024.

[C37] X. Wang, Y. He, X. Zhang, P. Zhou andX. Lou*, “An Efficient Hardware Volume Renderer for Convolutional Neural Radiance Fields,” in Proc., IEEE Int. Symp. Circuits Syst. (ISCAS), 2024.

[C36] Y. He andX. Lou*, “Density Estimation-based Effective Sampling Strategy for Neural Rendering,” in Proc., IEEE Int. Symp. Circuits Syst. (ISCAS), 2024.

[C35] H. Wang, X. Zhang andX. Lou*, “A Multi-scale Block PatchMatch-based Unified Algorithm for Efficient 6-D Vision Processing,” in Proc., IEEE Int. Symp. Circuits Syst. (ISCAS), 2024.

[C34] C. Pang, W. Zhou, H. Li, X. Zhang and X. Lou*, “Feature Map Guided Adapter Network for Object Detection in Low-light Conditions,” in Proc., IEEE Int. Symp. Circuits Syst. (ISCAS), 2024.

[C33] Y. Gu, Q. Wu, Z. Yuan, X. Zhang, W. Su Y. Zhang and X. Lou*, “An FPGA Accelerator for 3D Cone-beam Sparse-view Computed Tomography Reconstruction”, in Proc., IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2024.

[C32] L. Dai, H. Zhu, B. Yuan, C. Yang Y. Wang andX. Lou*, “Low-latency High-throughput Multi-precision Fused Floating-point Division and Square-root Unit Design,” in Proc.  International VLSI Symposium on Technology, Systems and Applications (VLSI TSA), 2024.

[C31]Z. Yuan, B. Yuan, Y. Gu, Y. Zheng, Y. He, X. Wang, C. Rao, P. Zhou, J. Yu andX. Lou*, “A 0.59μJ/pixel High-throughput Energy-efficient Neural Volume Rendering Accelerator on FPGA,” in Proc.  IEEE Custom Integrated Circuits Conference (CICC), 2024.

[C30]L. Dai, B. Yuan, C. Yang and X. Lou*, “Error Analysis for Fused Floating-Point Square-Root and Division Based on Goldschmidt Algorithm”, 2023 IEEE Interregional NEWCAS Conference (NEWCAS), Edinburgh, United Kingdom, 2023, pp. 1-5, doi: 10.1109/NEWCAS57931.2023.10198192.

[C29] H. Wan, C. Rao, Y. Zheng, P. Zhou and X. Lou*, “A Systolic Array with Activation Stationary Dataflow for Deep Fully-Connected Networks”, 2023 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), Hangzhou, China, 2023, pp. 1-5, doi: 10.1109/AICAS57966.2023.10168602.

[C28] M. Dong, W. Zhou, C. Pang, X. Zhang and X. Lou*, “Image Frequency Separation Residual Network for End-to-End Raw to RGB Mapping”, 2023 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), Hangzhou, China, 2023, pp. 1-5, doi: 10.1109/AICAS57966.2023.10168597.

[C27] H. Li, W. Zhou, X. Zhang andX. Lou*, “An Efficient Frequency Domain Vision Pipeline from RAW Images to Backend Tasks,” 2023 IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, USA, 2023, pp. 1-5, doi: 10.1109/ISCAS46773.2023.10182018.

[C26] H. Wan, C. Rao, Y. Zheng, P. Zhou andX. Lou*, “SME: A Systolic Multiply-accumulate Engine for MLP-based Neural Network,” 2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Shenzhen, China, 2022, pp. 270-274, doi: 10.1109/APCCAS55924.2022.10090307.

[C25] C. Rao, Y. Zheng, H. Wan, P. Zhou andX. Lou*, “An Energy Efficient Precision Scalable Computation Array for Neural Radiance Field Accelerator,” 2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Shenzhen, China, 2022, pp. 260-264, doi: 10.1109/APCCAS55924.2022.10090268. *Best Paper Nomination*

[C24] Y. Zheng, C. Rao, H. Wang, P. Zhou, J. Yu and X. Lou*, “RRAM-Based Neural Radiance Field Processor”, 2022 IEEE International System-on-Chip Conference (SOCC), Belfast, United Kingdom, 2022, pp. 1-5, doi: 10.1109/SOCC56010.2022.9908135

[C23] W. Hu, Y. Zhou, Y. Quan, Y. Wang and X. Lou*, “Cache-Locality Based Adaptive Warp Scheduling for Neural Network Acceleration on GPGPUs”, 2022 IEEE International System-on-Chip Conference (SOCC), Belfast, United Kingdom, 2022, pp. 1-6, doi: 10.1109/SOCC56010.2022.9908120.

[C22] K. Long, C. Rao, X. Zhang, W. Ye and X. Lou*, “FPGA Accelerator for Radar-Based Human Activity Recognition”, 2022 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), Incheon, Korea, Republic of, 2022, pp. 391-394, doi: 10.1109/AICAS54282.2022.9869908.

[C21] J. Geng, S. Wang and X. Lou*, “A Slide-Save Based Framework for Multi-Source DOA Extraction with Closely Spaced Sources,” 2022 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Singapore, Singapore, 2022, pp. 731-735, doi: 10.1109/ICASSP43922.2022.9746479.

[C20] L. Zhang, W. Zhou, X. Zhang andX. Lou*, “An End-to-end Computer Vision System Architecture,” 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Austin, TX, USA, 2022, pp. 2338-2342, doi: 10.1109/ISCAS48785.2022.9937670.

[C19] H. Wang, W. Zhou, X. Zhang andX. Lou*, “A 39pJ/label 1920x1080 165.7 FPS Block PatchMatch Based Stereo Matching Processor on FPGA,” 2022 IEEE Custom Integrated Circuits Conference (CICC), Newport Beach, CA, USA, 2022, pp. 1-2, doi: 10.1109/CICC53496.2022.9772830.

[C18] W. Liu, T. Wang, Y. Wang, X. Zhang andX. Lou*, “Stereo Point Cloud Refinement for 3D Object Detection,” 2021 IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), Penang, Malaysia, 2021, pp. 161-164, doi: 10.1109/APCCAS51387.2021.9687783.

[C17] S. Gao, H. Wang, T. Wang, Y. Wang, X. Zhang andX. Lou*, “Motion Assisted Video-based Stereo Matching,” 2021 IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), Penang, Malaysia, 2021, pp. 161-164, doi: 10.1109/APCCAS51387.2021.9687724.

[C16] J. Geng, S. Wang, J. Li, J. Li, X. Zhang andX. Lou*, “Robust Multi-Source Direction of Arrival Estimation Using a Single Acoustic Vector Sensor,” 2021 IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), Penang, Malaysia, 2021, pp. 161-164, doi: 10.1109/APCCAS51387.2021.9687767.

[C15] X. Zhang, W. Su, J. Li, J. Li and X. Lou*, “Spatial Non-Maximum Suppression for Object Detection using Correlation and Dynamic Thresholds,” 2021 18th International SoC Design Conference (ISOCC), Jeju Island, Korea, Republic of, 2021, pp. 264-265, doi: 10.1109/ISOCC53507.2021.9614023.

[C14] S. Wang, J. Geng and X. Lou*, Fully Convolutional Network-Based DOA Estimation with Acoustic Vector Sensor, 2021 IEEE Workshop on Signal Processing Systems (SiPS), Coimbra, Portugal, 2021, pp. 29-33, doi: 10.1109/SiPS52927.2021.00014.

[C13] J. Geng, S. Wang, J. Li, J. Li and X. Lou*, Reliable Intensity Vector Selection for Multi-source Direction-of-Arrival Estimation Using a Single Acoustic Vector Sensor, Interspeech 2021, 2137-2141, doi: 10.21437/Interspeech.2021-375.

[C12] H. Wang, S. Gao and X. Lou*, Multi-scale Slanted O(1) Stereo Matching Algorithm, 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea, 2021, pp. 1-5, doi: 10.1109/ISCAS51556.2021.9401179.

[C11] L. Zhang, W. Zhou, J. Li, J. Li andX. Lou*, “Histogram of Oriented Gradients Feature Extraction without Normalization,” 2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Ha Long, Vietnam, 2020, pp. 252-255, doi: 10.1109/APCCAS50809.2020.9301715.

[C10] W. Chen, Mo Huang andX. Lou*, “Sparse FIR Filter Design Based on Cascaded Compensation Structure,” 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 2019, pp. 1-5, doi: 10.1109/ISCAS.2019.8702703.

[C9] W. Chen, Mo Huang andX. Lou*, “A Branch-and-Bound Algorithm with Reduced Search Space for Sparse Filter Design,” 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Chengdu, China, 2018, pp. 329-332, doi: 10.1109/APCCAS.2018.8605638.

[C8]S. T.Li，W. B. Ye, H. W.  Liang, X. F. Pan,X. Lou and X. J. Zhao, “K-SVD Based Denoising Algorithm for DoFP Polarization Image Sensors,” 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018, pp. 1-5, doi: 10.1109/ISCAS.2018.8350922.

[C7]X. Lou* and W. Ye, “Low Complexity and Low Power Multiplierless FIR Filter Implementation,” 2017 IEEE 12th International Conference on ASIC (ASICON), Guiyang, China, 2017, pp. 596-599, doi: 10.1109/ASICON.2017.8252546.

[C6] Y. W, Y. Hong, W. L. Goh, Kevin T. C. Chai, X. LouandW. B. Ye, “A Passively Compensated Capacitive Sensor Readout with Biased Varactor Temperature Compensation and Temperature Coherent Quantization,” 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, USA, 2017, pp. 1-4, doi: 10.1109/ISCAS.2017.8050416.

[C5]X. Lou*, W. Ye and Y. J. Yu, “Investigation on Power Consumption of Product Accumulation Block for Multiplierless FIR Filters”, 2017 22nd International Conference on Digital Signal Processing (DSP), London, UK, 2017, pp. 1-5, doi: 10.1109/ICDSP.2017.8096107.

[C4] W. Ye*, X. Lou and Y. J. Yu, “Design of High-speed Multiplierless Linear-phase FIR filters”, 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, 2015, pp. 2964-2967, doi: 10.1109/ISCAS.2015.7169309.

[C3]X. Lou*, Y. J. Yu and P. K. Meher, “Fine-grained Pipelining for Multiple Constant Multiplications”, 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, 2015, pp. 966-969, doi: 10.1109/ISCAS.2015.7168796.

[C2]X. Lou* and Y. J. Yu, “Area-Time Efficient Realization of Multiple Constant Multiplication”, 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, 2015, pp. 962-965, doi: 10.1109/ISCAS.2015.7168795.

[C1]X. Lou*, Y. J. Yu and P. K. Meher, “High-speed multiplier block design based on bit-level critical path optimization,” 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, VIC, Australia, 2014, pp. 1308-1311, doi: 10.1109/ISCAS.2014.6865383.