上海翰慧微电子有限公司（Rface）是成立于2019年的跨国半导体设计公司RFACE TECHNOLOGY LTD.的中国分公司。其总部位于香港，在大中华，美国和德国设有分公司。公司拥有一支来自世界各地的富有创新精神的芯片设计团队，专长于射频/模拟设计和数字信号处理，着重在研发前沿的科技产品，技术标准包括低功耗，低成本，少外围器件的IoT (L3/LoRa), UWB 和 BLE等。也规划于2022年开始研发FMCW Lidar驱动芯片和算法。
Rface的核心技术团队由一位美国通信领域的院士（IEEE Fellow,擅长无线通信领域系统架构和算法），一位前美国博通（Broadcom）公司科学家级及技术副总监的模拟射频设计师，一位前台湾瑞昱（Realtek）WiMedia UWB SoC高级设计师领衔组成。Rface致力于成为一家全球领先的，可提供高集成高性能的，以创新的RF CMOS收发机技术和数字信号处理技术为特色的，半导体产品设计公司。
Rface现因业务发展需要，面向社会、应届毕业生、实习生诚聘如下岗位。薪资待遇高于行业平均水平，全员持股！
热忱欢迎有志于前沿高端自主可控射频数模混合芯片的优秀人才加盟！
工作地点：上海浦江镇陈行公路2168号智慧广场12栋（8号线浦江镇站直达）
简历投递邮箱：jun.yang@rfacetech.com（杨老师）
岗位一：Digital Design Engineer
The Digital Design Engineer's primary job function is to work with other team members to design and develop the digital modules from the concept to tape out or release for FPGA prototype.
Responsibilities:
• The position requires experience in all aspects of SoC design flow. Specifically, the SoC Design Engineer will own all aspects of a SoC from design to implementation.
Requirements：
• B.S. or M.S. in Electrical Engineering or equivalent.
• Expertise in Verilog and System Verilog for low power and testability.
• Experience with the full design cycle for ASICs or FPGAs.
• RTL synthesis and DFT / MBIST insertion.
• Expertise in UPF low power intent development.
• Interfacing with Physical Design team to support floor planning, timing constraints, ECO.
• Timing closure using STA tool.
• Logic Equivalency checking.
岗位二：SoC ARM IPs Design and Integration Engineer
The primary job function is to work with other team members to define architecture, design, and verify wireless SOC containing wireless transceivers, ARM Cortex M and other IPs.
Requirements：
• B.S. or M.S. in Electrical Engineering or equivalent.
• Expertise in Verilog and System Verilog for low power and testability design.
• Knowledge and experience of digital design techniques, including flow control, arbitration, FIFO, ARM Cortex CPU architecture, AXI / AHB bus architecture & protocols, serial interface design concepts (PCI-E, QSPI, I2C, etc…), FIFO, DMA, embedded memory (SRAM, OTP, etc…).
• Experience of ASIC low power design techniques including multiple supply domains and management, dynamic power/clock scaling, power analysis, UPF, VCLP. knowledge of how to drive the power down through all aspects of development, including chip architecture, micro-architecture, RTL design, and physical design.
• Hardware and firmware co verifications. Synthesis using Synopsys or Cadence tools.
岗位三：RF/Analog IC Design Engineer
Implement CMOS transceiver from specification to architectural and circuit blocks design and final product.
Responsibilities：
• Design and Simulate pre/post-layout of RFIC blocks, such as LNA, mixer, PA, VCO, Integer/Fractional N PLL/frequency synthesizer in CMOS.
• Able to use at least one EM tool to design/simulate the on-chip RF devices, such as inductors, capacitors and interconnectors, and their interactions.
• Design and Simulate pre/post-layout of Analog IC such as various types of data converters (ADC/DAC, Nyquist and Oversampled), PGA, Filters (continuous/discrete time), and power management circuit such as LDO and DC/DC in CMOS.
• Work with custom IC layout designer in floor planning, running LVS/DRC and perform parasitic extraction for post layout simulation.
• Propose devise test plan and test/debug the IC after tapeout.
• Behavior modeling using Matlab/Simulink or VerilogA for analog/RF systems or blocks.
Requirements：
• Master’s degree and 5 years’ experience with 2+ successful productions required; PhD preferred.
• Knowledge about communication systems, tradeoffs among various transceiver architectures, RF system design and layout skill.
• Familiarity with RF testing and Proficiency in the use of network analyzer, signal generators, spectrum analyzers, oscilloscope.
岗位四：Wireless System Design Engineer
Design and implement wireless transceiver and modem from specification, architectural, blocks, prototype to final product.
Responsibilities：
• Develop physical-layer algorithm reference models for prototypes of IOT, UWB, and 5G wireless modem.
• Model, simulate, optimize, and verify physical-layer digital modem systems with Python, Matlab, or C/C++ .
• Model and Simulate various baseband functional blocks such as AGC, AFC, mixer, filters, FFT, correlators, delta-sigma modulations, Frequency and timing synchronization, Channel Estimation and Equalization, Clock and carrier recovery, RF and Wireless Channels impairments modeling, and channel coding/FEC etc.
• Characterize fixed-point performance and optimize fixed-point algorithms to improve performance, latency, RTL area, etc.
• Support digital design, firmware, and RF teams with verification.
Requirements：
• Master’s degree, PhD preferred.
•Knowledge of communication systems, physical layer baseband modem algorithms.
• Experience with simulation & modeling of communications systems.
• Experience with one OR more of the following: Python C/C++, Matlab, or other simulation & modeling tools/language.
沪公网安备 31011502006855号
