A Statistical Methodology for Noise Sensor Placement and Full-Chip Voltage Map Generation

Xiaochen Liu, Shupeng Sun, Pingqiang Zhou, Xin Li and HaifengQian, "A Statistical Methodology for Noise Sensor Placement and Full-ChipVoltage Map Generation," Proceedings of the ACM/EDAC/IEEE DesignAutomation Conference (DAC), pp. 1-6, June 2015.

Abstract:  Noise margin violation, also known as voltageemergency induced by continuously reducing noise margin and increasingmagnitude of current swings, is becoming a severe threat to the correctexecution of applications in processors. Noise sensors can be placed in thenon-function area of processors to detect such emergencies by monitoringruntime voltage fluctuations. In this work, we aim to accurately predict thevoltage droops using a small set of sensors. We achieve our goal in two steps:We first propose a methodology via group lasso approach to select the optimalset of noise sensors, then build a practical model via ordinary least-squaresfitting approach to predict the voltage in the function area of the chip, usingthe selected sensors in non-function area. Experiment results show that whencompared to the full-chip voltage transient simulation, the prediction error ofour model is much less than 0.01, and compared to prior work, our approach canachieve better error rates of voltage emergency detection (less than half).

About the conference DAC (https://dac.com/):

The Design Automation Conference (DAC) is recognized as theflagship conference for design and automation of electronic systems. It issponsored by the Association for Computing Machinery (ACM), the ElectronicDesign Automation Consortium (EDA Consortium), and the Institute of Electricaland Electronics Engineers (IEEE), and is supported by ACM's Special InterestGroup on Design Automation (SIGDA).