Aggressive Design Reuse for Ubiquitous and Hardware-Patchable Secure Chips – From Physical Design to On-Chip Machine Learning

Publisher：闻天明Release Time：2022-11-22Number of visits：3205

Speaker:       Massimo Alioto, National University of Singapore

Time:            16:00-17:00  Nov.23.2022

Host:            Yajun Ha

Loction:          SIST 1A 200

 

Abstract:    

Divide-and-conquer design methodologies facilitate building block design, but conflict with basic security requirements, while also precluding opportunities for efficient system integration and inexpensive embedment of security features. At the same time, the insertion of security primitives as standalone blocks is inherently additive in terms of area, power, design effort and integration effort, limiting their embeddability in low-cost devices (i.e., the vast majority of the upcoming trillion chips for the Internet of Things). As further limitation of conventional approaches to security enforcement in silicon chips (e.g., against side-chanel attacks), the discovery of hardware vulnerabilities cannot be followed by later hardware fixes as we are used to do with software systems. In this keynote, the road towards ubiquitous hardware security is pursued from a primitive design perspective, designing PUFs and TRNGs that are inherently immersed in existing memory arrays and logic fabrics, and breaking the boundaries of traditional system partitioning. The new concept of hardware patching is also discussed, where circuit flexibility is introduced to make silicon chips able to evolve over time and counteract newly discovered vulnerabilities through learning based physical protection mechanisms.

 

Bio:    

Massimo Alioto is a Professor at the ECE Department of the National University of Singapore, where he leads the Green IC group, the Integrated Circuits and Embedded Systems area, and the FD-fAbrICS center on intelligent&connected systems. Previously, he held positions at the University of Siena, Intel Labs, University of Michigan Ann Arbor, University of California Berkeley, EPFL. He is (co)author of 350 publications on journals and conference proceedings, and six books. His primary research interests include ultra-low power and self-powered systems, green computing, circuits for machine intelligence, hardware security, and emerging technologies. He is the Editor in Chief of the IEEE Transactions on VLSI Systems, and was Deputy Editor in Chief of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems. He is/was Distinguished Lecturer for the IEEE Circuits and Systems and Solid-State Circuits Society. He served as Guest Editor of numerous journal special issues (e.g., JSSC, TCAS-I, TCAS-II, JETCAS), Technical Program Chair of several IEEE conferences (e.g., ISCAS, SOCC, PRIME, ICECS), and TPC member (ISSCC, ASSCC). Prof. Alioto is an IEEE Fellow.