Pingqiang Zhou
Vice Dean, Associate Professor
Graduated School:Ph.D., University of Minnesota, Twin Cities, USA
Tel:(021) 20685084
Office:Room 1A-219, SIST Building
Research Interests
Biography
Selected Publications

RESEARCH INTERESTS

  • EDA (electronic design automation)

  • AI chip

  • Computer architecture


BIOGRAPHY

Pingqiang Zhou is currently a tenured associate professor at SIST and serves as the vice dean in charge of undergraduate education.

Prior to joining ShanghaiTech, he was with the IBM T. J. Watson Research Center Yorktown Heights NY USA as a research intern in 2011 and with the University of Minnesota as a Post-Doctoral Researcher from 2012 to 2013. He was also with the Department of Electrical Engineering & Computer Sciences at University of California, Berkeley as a visiting scholar in 2015. His research interests include EDA, machine learning/deep learning for IC design, AI chip and computer architecture. He has published more than 50 internationally peer-reviewed journal and conference papers on these topics. He serves as the Associate Editor for ACM SIGDA Newsletter and has been serving/served on the technical committees of more than 10 international conferences. He received the B. Tech. degree from Nanjing University of Posts and Telecommunications in 2005, the M. Eng. degree from Tsinghua University in 2007 and the Ph.D. degree from University of Minnesota, Twin Cities in 2012.


SELECTED PUBLICATIONS

  1. Zhang, C., and Zhou P., A Quantized Training Framework for Robust and Accurate ReRAM-based Neural Network Accelerators, in Proceedings of the IEEE Asia and South Pacific Design Automation Conference, pp.43-48, 2021.

  2. Ma Y. and Zhou P., Efficient Techniques for Training the Memristor-based Spiking Neural Networks Targeting Better Speed, Energy and Lifetime, in Proceedings of the IEEE Asia and South Pacific Design Automation Conference, pp.390-395, 2021.

  3. Yang Y., Chen Z., Liu Y., Ho T.-Y., Jin Y. and Zhou P., How Secure is Split Manufacturing in Preventing Hardware Trojan?, ACM Transactions on Design Automation of Electronic Systems. Vol. 25, No. 2, pp. 1-23, 2020.

  4. Liu Y. and Zhou P., Defending Against Adversarial Attacks in Deep Learning with Robust Auxiliary Classifiers Utilizing Bit Plane Slicing, in Proceedings of the IEEE Asian Hardware Oriented Security and Trust Symposium, pp.1-4, 2020.

  5. Wang, L., Wang, L., Shang, D., Zhuo, C., and Zhou, P., “Optimization of switched-capacitor DC-DC converters in heterogeneous multicore systems”, in Proceedings of the Design, Automation, and Test in Europe Conference, 2019.

  6. Li, Y., Zhuo, C., and Zhou, P., “A Cross-Layer Framework for Temporal Power and Supply Noise Prediction”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018.

  7. Gao, W., Qian, Z., and Zhou, P., “Reliability-and performance-driven mapping for regular 3D NoCs using a novel latency model and Simulated Allocation”, Integration, 2018.

  8. Liu, Y., Chen, X., Kadambi, D., Bari, A., Li, X., Hu, S., and Zhou, P., “Dependable Visual Light-Based Indoor Localization with Automatic Anomaly Detection for Location-Based Service of Mobile Cyber-Physical Systems”, ACM Transactions on Cyber-Physical Systems, vol. 3, no. 1, p. 5, 2018.

  9. Cai, X., Yin, J., and Zhou, P., “An orchestrated NoC prioritization mechanism for heterogeneous CPU-GPU systems”, Integration, 2018.

  10. Liu, X., Sun, S., Li, X., Qian, H., & Zhou, P., “Machine learning for noise sensor placement and full-chip voltage emergency detection”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 3, pp. 421-434, 2017.

  11. Liu, X., Sun, S., Zhou, P.,  Li, X., and Qian, H., “A Statistical Methodology for Noise Sensor Placement and Full-Chip Voltage Map Generation”, in Proceedings of the ACM/EDAC/IEEE Design Automation Conference, pp. 1-6, 2015.

  12. Zhou, P., Paul, A., Kim, C. H., & Sapatnekar, S. S., “Distributed on-chip switched-capacitor DC–DC converters supporting DVFS in multicore systems”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 9, pp. 1954-1967, 2014.

  13. Yin, J., Zhou, P., Sapatnekar, S. S., & Zhai, A., “Energy-efficient time-division multiplexed hybrid-switched noc for heterogeneous multicore systems”, in Proceedings of Parallel and Distributed Processing Symposium, 2014 IEEE 28th International, pp. 293-303, May 2014.

  14. Zhou, P., Ma, Y., Li, Z., Dick, R. P., Shang, L., Zhou, H., ... & Zhou, Q., “3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits”, in Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, pp. 590-597, November 2007.