Yajun Ha
Professor
Graduated School:Ph.D., KU Leuven, Belgium
Tel:(021) 20685371
Office:Room 3-316, SIST Building
Research Interests
Biography
Selected Publications

RESEARCH INTERESTS

  • FPGA architectures, tools, and applications

  • Ultra low power circuits and systems

  • Embedded system design and methodology for applications in hardware security, smart vehicles and machine learning


BIOGRAPHY

Yajun Ha (S’98–M’04–SM’09) received the B.S. degree from Zhejiang University, Hangzhou, China, in 1996, the M.Eng. degree from the National University of Singapore, Singapore, in 1999, and the Ph.D. degree from Katholieke Universiteit Leuven, Leuven, Belgium, in 2004, all in electrical engineering.

He is currently a Professor at ShanghaiTech University, Director of Shanghai Engineering Research Center of Energy Efficient and Custom AI IC, Director of ShanghaiTech Post-Moore Device and Integrated System Center. Before this, he was a Scientist and Director, I2R-BYD Joint Lab at Institute for Infocomm Research, Singapore, and an Adjunct Associate Professor at the Department of Electrical & Computer Engineering, National University of Singapore. Prior to this, he was an Assistant Professor with National University of Singapore.

His research interests include reconfigurable computing, ultra-low power digital circuits and systems, embedded system architecture and design tools for applications in robots, smart vehicles and intelligent systems. He has published more than 120 internationally peer-reviewed journal/conference papers on these topics.

He has served a number of positions in the professional communities. He serves as the Editor-in-Chief for the IEEE Trans. on Circuits and Systems II: Express Briefs (2020–2021), the Associate Editor for the IEEE Trans. on Circuits and Systems I: Regular Papers (2016–2019), the Associate Editor for the IEEE Trans. on Circuits and Systems II: Express Briefs (2011–2013), the Associate Editor for the IEEE Trans. on Very Large Scale Integration (VLSI) Systems (2013–2014), and the Journal of Low Power Electronics (since 2009). He has served as the TPC Co-Chair of ISICAS 2020, the General Co-Chair of ASP-DAC 2014; Program Co-Chair for FPT 2010 and FPT 2013; Chair of the Singapore Chapter of the IEEE Circuits and Systems (CAS) Society (2011 and 2012); Member of ASP-DAC Steering Committee; and Member of IEEE CAS VLSI and Applications Technical Committee. He has been the Program Committee Member for a number of well-known conferences in the fields of FPGAs and design tools, such as DAC, DATE, ASP-DAC, FPGA, FPL and FPT. He is the recipient of several IEEE/ACM Best Paper Awards. He is a senior member of IEEE.


SELECTED PUBLICATIONS

  1. J. Chen, W. Zhao, Y. Wang, Y. Shu, W. Jiang, and Y. Ha, “A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations”, IEEE Transactions on VLSI SystemsAccepted for publication, 2022.

  2. F. Chen, H. Yu, W. Jiang and Y. Ha, “Quality Optimization of Adaptive Applications via Deep Reinforcement Learning in Energy Harvesting Edge Devices”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Accepted for publication, 2022.

  3. W. Jiang, H. Yu , H. Zhang, Y. Shu, R. Li, J. Chen and Y. Ha, “FODM: A Framework for Accurate Online Delay Measurement Supporting All Timing Paths in FPGA”, IEEE Transactions on VLSI Systems, Vol 30, No. 4, pp502-514, Apr 2022.

  4. G. Yan, X. Liu , F. Chen, H. Wang and Y. Ha, “Ultra-Fast FPGA Implementation of Graph Cut Algorithm With Ripple Push and Early Termination”, IEEE Transactions on Circuits and Systems I, Vol 69, No. 4, pp1532-1545, Apr, 2022.

  5. Z. Liao, D. Jiang, X. Liu, A. Velten, Y. Ha and Xin Lou, “FPGA Accelerator for Real-Time Non-Line-of-Sight Imaging”, IEEE Transactions on Circuits and Systems I, Vol 69, No. 2, pp721-734, Feb 2022.

  6. Q. Deng, H. Sun, F. Chen, Y. Shu, H. Wang and Y. Ha, “An Optimized FPGA-Based Real-Time NDT for 3D-LiDAR Localization in Smart Vehicles”, IEEE Transactions on Circuits and Systems II, Vol 68, No. 9, pp1644-1648, Sep 2021.

  7. H. Yu, Y. Ha, B. Veeravalli, F. Chen and H. El-Sayed, “DVFS-Based Quality Maximization for Adaptive Applications with Diminishing Return”, IEEE Transactions on Computers, Vol 70, No 5, pp803-816, May 2021.

  8. H. Zhang, Y. Shu, W. Jiang, Z. Yin, W. Zhao, and Y. Ha, “A 55nm, 0.4V 5526-TOPS/W Compute-in-Memory Binarized CNN Accelerator for AIoT Applications”, IEEE Transactions on Circuits and Systems II, Vol 68, No. 5, pp1644-1648, May 2021.

  9. J. Chen, W. Zhao, Y. Wang and Y. Ha, “Analysis and Optimization Strategies Toward Reliable and High Speed 6-T Compute SRAM”,IEEE Transactions on Circuits and Systems I, Vol 68, No. 4, pp1520-1531, 2021.

  10. X. Liu, F. Chen, R. K. Muhamad, D. Blinder, D. Nikolova, F. Catthoor, Y. Ha, “Bitwidth-Optimized Energy-Efficient FFT Design via Scaling Information Propagation”, Proc. of Design Automation Conference (DAC’21), Dec 2021.

  11. W. Jiang, H. Yu, X. Liu, H. Sun, R. Li and Y. Ha, “TAIT: One-Shot Full-Integer Lightweight DNN Quantization via Tunable Activation Imbalance Transfer”, Proc. of Design Automation Conference (DAC’21), Dec 2021.

  12. A. Li, H. Yu, W. Jiang and Y. Ha, “DVFS-Based Scrubbing Scheduling for Reliability Maximization on Parallel Tasks in SRAM-based FPGAs”. Proc of Design Automation Conference, USA, July 2020.