SIST Undergraduate Student Published a Paper in ACM/IEEE DAC Conference

Li Rui, a senior undergraduate student from the research group of Professor Ha Yajun, had a paper accepted by ACM / IEEE Design Automation Conference (DAC 2020) (Paper title: DVFS-Based Scrubbing Scheduling for Reliability Maximization on Parallel Tasks in SRAM-based FPGAs) as the first author. This is Li Rui’s second scientific paper accepted by international conferences in this year. His first paper was accepted by the International Symposium on Circuits and Systems (ISCAS 2020), the flagship conference of the IEEE Circuits and Systems Society, as the second author. 


Static RAM (SRAM) based Field programmable gate array (FPGA) is considered as a potential high efficiency computing platform for applications on satellites and smart vehicles. It has powerful computing power and performance and has the flexibility of reconfigurable circuits. At the same time, FPGA has the significant advantages of low cost and fast time-to-market compared to dedicated chip ASIC. But in terms of reliability, SRAM-based FPGAs were not originally designed for high-reliability scenarios, thus data stored in SRAM can be easily affected by the external environment in a high-radiation environment. In order to solve this problem, Ha Yajun's group proposed a new FPGA scrubbing mechanism based on dynamic voltage frequency adjustment (DVFS) and developed a set of optimization algorithms to maximize the chance of SRAM being scrubbed before being executed. Compared with the Triple Module Redundancy mechanism, the scrubbing mechanism utilizes the programmability of FPGA, thus avoiding a lot of hardware redundancy. Compared with other latest researches, this work can improve the system reliability by 36.1% and basically makes SRAM-based FPGAs applicable to areas with high requirements for circuit reliability, such as aerospace and smart vehicles, without hardware overhead.


The method proposed in the article


The ACM / IEEE DAC conference is one of the most recognized international conference in the field of Electronics Design Automation (EDA) and embedded systems. The acceptance rate in the past two years is about 20%. Every year, the DAC conference attracts many scientists, researchers, and industry professional to exchange their work and provide ideas and inspiration for future research.


ACM / IEEE DAC Conference Poster


This year, many articles of Professor Ha Yajun’s research group were accepted by top international conferences and journals. These articles were all completed by ShanghaiTech university. Professor Ha Yajun founded the Reconfigurable and Intelligent Hardware Laboratory and served as Director of the Post-Moore Microelectronics Integrated Circuit Center (PMICC) since he joint ShanghaiTech in 2017 with a present research team of around 15 members including doctoral students, master students, and undergraduates. Over the past few years, the team has focused on FPGA architectures and design tools, ultra-low-power digital circuit and system design, custom computing system design for smart vehicles and robots, and published many results in top international journals and conferences. The laboratory spent great effort to cultivate students, especially to improve the critical and innovative thinking capability of all team members including undergraduates. From this summer, Li Rui will begin his postgraduate study in Professor Ha Yajun's research group.

Li Rui