Yajun Ha, Professor

Yajun Ha, Professor

Tel:  (021) 20685371
Email: hayj@@shanghaitech.edu.cn
Office: Room 1D-401A, SIST Building
Major: EE
Website: http://faculty.sist.shanghaitech.edu.cn/faculty/hayj
Education: Ph.D., KU Leuven, Belgium
Yajun Ha Research Group Recruitment (Click Here)


  • FPGA architectures, tools, and applications

  • Ultra low power circuits and systems

  • Embedded system design and methodology for applications in hardware security, smart vehicles and machine learning


Yajun Ha is currently the PMICC Director, the Academic Affairs Committee Director and the Deputy director of Faculty Search Committee.

Yajun Ha is professor at Shanghaitech University, China. Before this, he was a Scientist and Co-Director, I2R-BYD Joint Lab at Institute for Infocomm Research, Singapore, and an Adjunct Associate Professor at the Department of Electrical & Computer Engineering, National University of Singapore. Prior to this, he was an Assistant Professor with National University of Singapore. He received his Ph.D. degree from Katholieke Universiteit Leuven (KULeuven), Leuven, Belgium, in 2004 and worked at the same period as a researcher with the Inter-University MicroElectronics Center (IMEC), Leuven, Belgium. 

His research interests are related to highly energy-efficient computing, especially in reconfigurable computing, ultra-low power digital circuits and systems, and embedded system architecture and design tools for applications in robot, smart vehicles and machine learning and so on. He has published more than 100 internationally peer-reviewed journal/conference papers on these topics.

He has served a number of positions in the professional communities. He serves as the Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-PART I: Regular Papers (2016–2017), the Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-PART II: EXPRESS BRIEFS (2011–2013), the Associate Editor for the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2013–2014), and the Journal of Low Power Electronics (since 2009). He has served as the General Co-Chair of ASP-DAC 2014; Program Co-Chair for FPT 2010 and FPT 2013; Chair of the Singapore Chapter of the IEEE Circuits and Systems (CAS) Society (2011 and 2012); Member of ASP-DAC Steering Committee; and Member of IEEE CAS VLSI and Applications Technical Committee. He has been the Program Committee Member for a number of well-known conferences in the fields of FPGAs and design tools, such as DAC, DATE, ASP-DAC, FPGA, FPL and FPT.


  1. Yuanyong Luo, Yuxuan Wang, Yajun Ha, et al., “Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation with Arbitrary Fixed Base”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 9, pp. 2156-2169, 2019.

  2. W. Jiang, H. Yu, Y. Ha, “Enabling Fine-Grained Dynamic Voltage and Frequency Scaling in SDSoC”, in Proceedings of 32nd IEEE SoCC, Singapore, 2019.

  3. X. Liu, F. Chen, Y. Ha, “Area Efficient Box Filter Acceleration by Parallelizing with Optimized Adder Tree”, in Proceedings of ISVLSI 2019, 2019.

  4. H. Sun, Y. Luo, Y. Ha, et al., “A Linear Approximation Method with Controllable Absolute Error for the Efficient Implementation of Transcendental Functions”, IEEE Transactions on Circuits and Systems I, 2019.

  5. W. Zhao, B. Sun, J. Chen, Y. Ha, “AxC-CS: Approximate Computing for Hardware Efficient Compressed Sensing Encoder Design”, in Proceedings of 32nd IEEE SoCC, Singapore, 2019.

  6. W. Jiang, H. Yu, X. Liu, Y. Ha, “A Fast and Efficient FPGA Platform with Fine-grained DVFS Support Using SDSoC”, in Proceedings of ICECS 2019, 2019.

  7. Liang Yun, Wang Shuo, Mitra Tulika, Ha Yajun, “Analytical Two-Level Near Threshold Cache Exploration for Low Power Biomedical Applications”, in Proceedings of Advanced Computer Architecture, Yingkou, China, 2018.

  8. Huang Tian, Zhu, Yongxin, Ha Yajun, et al, “A Hardware Pipeline with High Energy and Resource Efficiency for FMM Acceleration”, ACM Transactions on Embedded Computing Systems, vol. 17, no. 2, 2018.

  9. Wang Yi, Ha Yajun, “A DFA-Resistant and Masked PRESENT with Area Optimization for RFID Applications”, ACM Transactions on Embedded Computing Systems, vol. 16, no. 4, 2017.

  10. Zhao Wenfeng, Li Ang, Wang Yi, et al, “Analysis and Design of Energy-Efficient Data-Dependent SRAM”, in Proceedings of 2017 IEEE 12th International Conference on ASIC (ASICON), Guiyang, 2017.