Xin Lou, Assistant Professor

Xin Lou, Assistant Professor

Tel:  (021) 20685375
Email: louxin@@shanghaitech.edu.cn
Office: Room 1D-301E, SIST Building
Major: EE
Website:
Education: Ph.D., Nanyang Technological University, Singapore
Xin Lou Research Group Recruitment (Click Here)

RESEARCH INTERESTS

  • Digital FIR filter design and implementation

  • Energy-efficient VLSI digital signal processing circuits and systems 

  • Smart vision circuits and systems


BIOGRAPHY

Dr. Lou obtained his bachelor’s degree in Electronic Science and Technology from Zhejiang University (ZJU), China, in 2010 and Master’s degree in System-on-Chip Design from Royal Institute of Technology (KTH), Sweden, in 2012 and PhD degree in Electrical and Electronic Engineering from Nanyang Technological University (NTU), Singapore, in 2016. Then he joined VIRTUS, IC Design Centre of Excellence at the same university as a research scientist. In Feb. 2017, Dr. Lou joined the School of Information Science and Technology, ShanghaiTech University as an assistant professor, PI.


SELECTED PUBLICATIONS

  1. Chen Wangqian, Mo Huang and Xin Lou, “Design of Sparse FIR Filters with Reduced Effective Length”, IEEE Transactions on Circuits and Systems I: Regular Papers, 2018.

  2. Chen Wangqian, Mo Huang and Xin Lou, “A Branch-and-Bound Algorithm with Reduced Search Space for Sparse Filter Design”, in Proceedings of 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2018.

  3. Li S., Ye W., Liang H., Pan X., Lou X. and Zhao, X., “K-SVD Based Denoising Algorithm for DoFP Polarization Image Sensors”, in Proceedings of 2018 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, May 2018.

  4. X. Lou, Y. J. Yu and P. K. Meher, “Lower Bound Analysis and Perturbation of Critical Path for Area-Time Efficient Multiple Constant Multiplications”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol 36, no. 2, pp. 313-324, February 2017.

  5. P.K. Meher and X. Lou, “Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for GF(2^m) Based on Irreducible All-One Polynomials”, IEEE Transactions on Circuits and Systems I, vol 64, no. 2, pp. 313-324, February 2017.

  6. X. Lou, Y. J. Yu and P. K. Meher, “Analysis and Optimization of Product-Accumulation Section for Efficient Implementation of FIR Filters”, IEEE Transactions on Circuits and Systems I, vol 63, no. 10, pp. 1701-1713, October 2016.

  7. X. Lou, Y. J. Yu and P. K. Meher, “Fine-Grained Critical Path Analysis and Optimization for Area-Time Efficient Realization of Multiple Constant Multiplications”, IEEE Transactions on Circuits and Systems I, vol 62, no. 3, pp. 863-872, March 2015.

  8. X. Lou, Y. J. Yu and P. K. Meher, “New Approach to the Reduction of Sign-extension Overhead for Efficient Implementation of Multiple Constant Multiplications”, IEEE Transactions on Circuits and Systems I, vol 62, no. 11, pp. 2695-2705, November 2015.