Post-Doctoral Researcher Xiangyu Zhang

Post-Doctoral Researcher Xiangyu Zhang

Tel:
Email :zhangxy10@@shanghaitech.edu.cn
Office:Room 1C-315, SIST Building
Research Group:Prof. Xin Lou's group

RESEARCH INTERESTS

Low-power hardware design for machine vision

Object detection system based on FPGA & ASIC platform

 

BIOGRAPHY

Dr. Xiangyu ZHANG received B.E. and B.A. degree in Electrical Engineering from Tianjin University and Economics from Nankai University in 2013. She received the master’s degree in electrical engineering from Hiroshima University in 2016, and the Ph.D. degree in system cybernetics from Hiroshima University in 2019. From May 2019, she joined the School of Information Science and Technology in ShanghaiTech University as a research fellow.Her research interests are in the area of object-detection integrated-circuit design, with special emphasis on sensor interfaces and raw image.

 

SELECTED PUBLICATIONS

[1] Zhang, X.*, An, F., Chen, L., Ishii, I., & Mattausch, H. J., “A Modular and Reconfigurable Pipeline Architecture for Learning Vector Quantization,” IEEE Transaction on Circuits and System I: Regular Papers (TCAS I),65(10), 3312-3325, Oct. 2018. (*Corresponding author)

[2] Zhang, X., An, F., Nakashima, I., Luo, A., Chen, L., Ishii, I., & Mattausch, H. J., “A Hardware-Oriented Histogram of Oriented Gradients Algorithm and Its VLSI Implementation,” Japanese Journal of Applied Physics (JJAP), 56(4S), 04CF01, Jan. 30, 2017.

[3] Zhang, X., An, F., Chen, L., & Mattausch, H. J., “Reconfigurable VLSI Implementation for Learning Vector Quantization with On-Chip Learning Circuit,” Japanese Journal of Applied Physics (JJAP), 55(4S), 04EF02, Mar. 03, 2016.

[4] An, F., Zhang, X., Luo, A., Chen, L., & Mattausch, H. J., “A Hardware Architecture for Cell-based Feature-Extraction and Classification Using Dual-Feature Space,” IEEE Transactions on Circuits and Systems for Video Technology (TCSVT), 28(10), 3086-3098, Oct. 2018.

[5] An, F., Zhang, X., Chen, L., & Mattausch, H. J., “A Memory-Based Modular Architecture for SOM and LVQ with Dynamic Configuration,” IEEE Transactions on Multi-Scale Computing Systems (TMSCS),2(4), 234-241, Oct. 20, 2016.