Research Projects Involved at University of Minnesota, Twin Cities and Tsinghua  University

 

  1.  1. An Integrated Design and CAD Approach for Efficient Power Delivery in Multicore Processors (NSF and SRC project,  2009/09-2013/01)

Reliable power delivery is being recognized as a major challenge in multicore processors due to unpredictable loads and large switching transients between cores. Supply levels are steadily falling with technology scaling which results in less voltage headroom, while the total current drawn by a chip is increasing, with sub-32nm technologies showing especially high leakage current levels. These trends lead to worsening on-chip power supply noise that can cause a circuit to fail to meet its specifications. Today, even in single-core chips, or chips with a small number of cores, the power delivery problem is already one of the hardest problems facing a designer. This issue becomes progressively worse for future multicore systems. The goal of this project is to develop concrete design and CAD techniques for novel on-chip power delivery in multicore processors.

Related publications:

  1. 1. Pingqiang Zhou, Vivek Mishra, and Sachin S. Sapatnekar, “Placement Optimization of Power Supply Pads Based on Locality,” The Design, Automation, and Test in Europe Conference (DATE), pp. 1655-1660, 2013.

  2. 2. Pingqiang Zhou, Bongjin Kim, Wonho Choi, Chris H. Kim, and Sachin S. Sapatnekar, “Optimization of On-Chip Switched-Capacitor DC-DC Converters for High-Performance Applications,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 263-270, 2012.

  3. 3. Pingqiang Zhou, Dong Jiao, Chris H. Kim, and Sachin S. Sapatnekar, “Exploration of On-Chip Switched-Capacitor DC-DC Converter for Multicore Processors Using a Distributed Power Delivery Network,” Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), pp.1-4, 2011.

  1. 2. Integrated Layout and Architectural Design for (3D) Multicore Platforms (SRC project, 2008/07-2011/08)

Process scaling and the critical reality of stringent power and thermal budgets have driven the growth of multicore systems. Homogeneous multicores consist of arrays of similar cores on the same die, while heterogeneous platforms integrate cores with different capacities, functionalities, or even different instruction set architectures, onto a single die. It is essential to design the cores, the communication network, and the memory system with the goal of optimizing system-level performance. The physical layout and topology of a multicore platform is closely related to architectural decisions, and design of these platforms must incorporate the close interaction between these two. This project develops dedicated CAD solutions that closely couple layout and architectural decisions to build optimized multicore platforms in both 2D and 3D IC paradigms.

Related publications:

  1. 1. Jieming Yin, Pingqiang Zhou, Sachin S. Sapatnekar, and Antonia Zhai, “Energy-Efficient Time-Division Multiplexed Hybrid NoC for Heterogeneous Multicore Systems,” Proceedings of the IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2014.

  2. 2. Pingqiang Zhou, Ping-Hung Yuh, and Sachin S. Sapatnekar, “Optimized 3D Network-on-Chip Design Using Simulated Allocation,” ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol.17, No.2, pp.1-19, 2012.

  3. 3. Jieming Yin, Pingqiang Zhou, Anup P. Holey, Sachin S. Sapatnekar, and Antonia Zhai, “Energy Efficient Non-Minimal Path On-chip Interconnection Network for Heterogeneous Systems,” Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp.57-62, 2012.
  4. 4. Pingqiang Zhou, Jieming Yin, Antonia Zhai, and Sachin S. Sapatnekar, “NoC Design and Performance Optimization,” SRC TECHCON, 2011.

  5. 5. Pingqiang Zhou, Jieming Yin, Antonia Zhai, and Sachin S. Sapatnekar, NoC Frequency Scaling with Flexible-Pipeline Routers, Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp.403-408, 2011.

  6. 6. Pingqiang Zhou, Ping-Hung Yuh, and Sachin S. Sapatnekar, “Application-Specific 3D Network-on-Chip Design Using Simulated Allocation,” Proceedings of the Asia-South Pacific Design Automation Conference (ASPDAC), pp.517–522, 2010.

  1. 3. CAD for 3D Integrated Circuits (09/2005-07/2008)

3D circuit technologies, with multiple tiers of active devices stacked on top of each other, represent a key approach to achieving increased levels of integration and performance. However, to reach their full potential, the technologies must overcome two significant limitations, related to on-chip thermal issue and reliable power delivery. Both issues ca

n be illustrated through a simple back-of-the-envelope calculation: A ktier 3D chip that stacks k similar chips could use k times as much current as a single 2D chip of the same footprint. However, the packaging technology is not appreciably different; with a similar heat sink, the on-chip temperature on such a 3D chip is k times higher than the 2D chip, and with a similar number of pins in the package, the current per pin is k times higher than the 2D case. The above analysis operates under very coarse assumptions (for example, a smart 3D designer may not stack k layers with identical power levels), and a more nuanced approach is necessary for a more accurate analysis – but the eventual conclusions that thermal and power delivery issues are important in 3D - are inescapable. The goal of this project is to develop novel CAD techniques for thermal optimization and reliable power delivery in 3D circuits.

Related publications:

  1. 1. Pulkit Jain, Pingqiang Zhou, Chris H. Kim, and Sachin S. Sapatnekar, “Thermal and Power Delivery Challenges in 3D ICs,” in Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures, Springer, Boston, MA, 2010. (Book chapter)

  2. 2. Yuchun Ma, Qiang Zhou, Pingqiang Zhou, and Xianlong Hong, “Thermal Impacts of Leakage Power in 2D/3D Floorplanning,” Journal of Circuits, Systems, and Computers (JCSC), Vol.19, No.7, pp.1483-1495, 2010.
  3. 3. Pingqiang Zhou, Karthikk Sridharan, and Sachin S. Sapatnekar, “Power Grid Optimization in 3D Circuits Using MIM and CMOS Decoupling Capacitors,” IEEE Design & Test (D&T), Vol.26, No.5, pp.15-25, 2009.

  4. 4. Pingqiang Zhou, Karthikk Sridharan, and Sachin S. Sapatnekar, “Congestion-Aware Power Grid Optimization for 3D Circuits Using MIM and CMOS Decoupling Capacitors,” Proceedings of the Asia-South Pacific Design Automation Conference (ASPDAC), pp.179–184, 2009.

  5. 5. Pingqiang Zhou, Jie Gu, Pulkit Jain, Chris H. Kim, and Sachin S. Sapatnekar, “Reliable Power Delivery for 3D ICs,” Sematech Workshop on Design and Test Challenges for 3D ICs, 2008.

  6. 6. Pingqiang Zhou, Yuchun Ma, Zhouyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, and Qiang Zhou, “3D-STAF: Scalable Temperature and Leakage Aware Floorplanning for Three-dimensional Integrated Circuits,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp.590–597, 2007.

  7. 7. Pingqiang Zhou, Yuchun Ma, Qiang Zhou, and Xianlong Hong, “Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning,” Proceedings of the IEEE International Conference on Computer-Aided Design and Computer Graphics (CAD&CG), pp.338–343, 2007.