Network on Chip (NoC) in Multicore Processors

Process scaling and the critical reality of stringent power and thermal budgets have driven the growth of multicore systems. Homogeneous multicores consist of arrays of similar cores on the same die, while heterogeneous platforms integrate cores with different capacities, functionalities, or even different instruction set architectures, onto a single die. It is essential to design the cores, the communication network, and the memory system with the goal of optimizing system-level performance.

We aims to develop dedicated CAD solutions to build optimized multicore platforms in 3D IC paradigms, using silicon photonics for on-chip global communication.

 
Fig. 1. A homogeneous multicore chip using NoC for inter-core communication.
 
Fig. 2. A heterogeneous multicore chip with both CPU and GPU cores.

 

 

 
Fig. 3. 3D heterogeneous integration.                                  Fig. 4. On-chip optical network [IBM].

Related publications:

  1. 1. Xiangwei Cai*, Jieming Yin and Pingqiang Zhou, "An Orchestrated NoC Prioritization Mechanism for Heterogeneous CPU-GPU Systems," the IEEE/ACM International Conference on Computer-Aided Design. (Under Review)
  2. 2. [CAD/CG] Kai Liao* and Pingqiang Zhou, "A Study about Task-Based DVFS Policy," in Proceedings of the IEEE International Conference on Computer-Aided Design and Computer Graphics, 2016.
  3. 3. [IPDPS] Jieming Yin, Pingqiang Zhou, Sachin S. Sapatnekar, and Antonia Zhai, “Energy-Efficient Time-Division Multiplexed Hybrid NoC for Heterogeneous Multicore Systems,” Proceedings of the IEEE International Parallel and Distributed Processing Symposium, pp. 293-303, 2014.