Publications Before 2013

Please be aware that although PDF files are provided as a courtesy for the publications listed below, many of them are copyrighted by the corresponding publishers.

Thesis
  1. 1. Pingqiang Zhou, “ Interconnect Design Techniques for Multicore and 3D Integrated Circuits,” Ph. D., University of Minnesota, 2012.

  2. 2. Pingqiang Zhou, “Research On 3D Force-Directed Floorplannning Algorithm (in Chinese),” M. E., Tsinghua University, Beijing, China, 2007.

 
Book Chapter
  1. 1. Pulkit Jain, Pingqiang Zhou, Chris H. Kim, and Sachin S. Sapatnekar, “ Thermal and Power Delivery Challenges in 3D ICs,”   in Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures, Springer, Boston, MA, 2010.


Journal
  1. 1. [TOADES] Pingqiang Zhou, Ping-Hung Yuh, and Sachin S. Sapatnekar, “Optimized 3D Network-on-Chip Design Using Simulated Allocation,” ACM Transactions on Design Automation of Electronic Systems, Vol.17, No.2, pp.1-19, 2012.

    2. [JCSC] Yuchun Ma, Qiang Zhou, Pingqiang Zhou, and Xianlong Hong, “Thermal Impacts of Leakage Power in 2D/3D Floorplanning,” Journal of Circuits, Systems, and Computers, Vol.19, No.7, pp.1483-1495, 2010.

    3. [D&T] Pingqiang Zhou, Karthikk Sridharan, and Sachin S. Sapatnekar, “Power Grid Optimization in 3D Circuits Using MIM and CMOS Decoupling Capacitors,” IEEE Design & Test,  Vol.26, No.5, pp.15-25, 2009.


Conference
  1. 1. [ICCAD] Pingqiang Zhou, Bongjin Kim, Wonho Choi, Chris H. Kim, and Sachin S. Sapatnekar, “Optimization of On-Chip Switched-Capacitor DC-DC Converters for High-Performance Applications,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 263-270, 2012.

  2. 2. [ICCAD] Jianxin Fang, Saket Gupta, Sanjay Kumar, Sravan Marella, Vivek Mishra, Pingqiang Zhou, and Sachin Sapatnekar, “Circuit Reliability: From Physics to Architectures (Embedded Tutorial),” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp.243-246, 2012.

  3. 3. [ISLPED] Jieming Yin, Pingqiang Zhou, Anup P. Holey, Sachin S. Sapatnekar, and Antonia Zhai, “Energy Efficient Non-Minimal Path On-chip Interconnection Network for Heterogeneous Systems,”Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design, pp.57-62, 2012.

  4. 4. [CICC] Pingqiang Zhou, Dong Jiao, Chris H. Kim, and Sachin S. Sapatnekar, “Exploration of On-Chip Switched-Capacitor DC-DC Converter for Multicore Processors Using a Distributed Power Delivery Network,”Proceedings of the IEEE Custom Integrated Circuits Conference, pp.1-4, 2011.

  5. 5. [ISLPED] Pingqiang Zhou, Jieming Yin, Antonia Zhai, and Sachin S. Sapatnekar,“NoC Frequency Scaling with Flexible-Pipeline Routers,“ Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design, pp.403-408, 2011.

  6. 6. [ASPDAC] Pingqiang Zhou, Ping-Hung Yuh, and Sachin S. Sapatnekar, “Application-Specific 3D Network-on-Chip Design Using Simulated Allocation,”Proceedings of the Asia-South Pacific Design Automation Conference, pp.517–522, 2010. (Nominated for Best Paper Award)

  7. 7. [ASPDAC] Pingqiang Zhou, Karthikk Sridharan, and Sachin S. Sapatnekar, “Congestion-Aware Power Grid Optimization for 3D Circuits Using MIM and CMOS Decoupling Capacitors,” Proceedings of the Asia-South Pacific Design Automation Conference, pp.179–184, 2009.

  8. 8. [ICCAD] Pingqiang Zhou, Yuchun Ma, Zhouyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, and Qiang Zhou, “3D-STAF: Scalable Temperature and Leakage Aware Floorplanning for Three-dimensional Integrated Circuits,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp.590–597, 2007.

  9. 9. [CAD/CG] Pingqiang Zhou, Yuchun Ma,Qiang Zhou, and Xianlong Hong, "Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning," Proceedings of the IEEE International Conference on Computer-Aided Design and Computer Graphics, pp.338–343, 2007.

 
Other Publications
  1. 1. Pingqiang Zhou, Jieming Yin, Antonia Zhai, and Sachin S. Sapatnekar, “NoC Design and Performance Optimization,” SRC TECHON, 2011.

  2. 2. Pingqiang Zhou, Jie Gu, Pulkit Jain, Chris H. Kim, and Sachin S. Sapatnekar, “Reliable Power Delivery for 3D ICs,” Sematech Workshop on Design and Test Challenges for 3D ICs, 2008.