About the Group                                                                       

The computer-aided design (CAD) group at ShanghaiTech University conducts research primarily in the area of CAD of VLSI circuits and systems: Our research work focuses on developing novel algorithms, techniques, and CAD software implementations to drive the design of future VLSI systems, which will consist of hundreds to thousands of heterogeneous cores performing operations in parallel, and will use advanced manufacturing technologies such as three-dimensional (3D) integration. Some specific problems that we are currently working on include machine learning for hardware design, power deliveryon-chip communication network, indoor localization and hardware security

Openings: Our group is currently seeking strong candidates to fill a few openings for research positions. We are also recruiting 2 - 3 academic graduate students for Fall 2017. Click here for more details about the positions.

Unique opportunities for our group members:

1) They have the opportunities to work on joint research projects with some of the top research groups in the world. For instance, the BSIM group lead by Prof. Chenming Hu@UC Berkeley and Prof. Xin Li's group@Duke University. See more about our collaborators at http://sist.shanghaitech.edu.cn/faculty/zhoupq/people.collaborators.html.

2) Excellent members also have the opportunities to visit our partner groups for either a long or short term. For instance, in Spring 2015 we sent one student to visit Prof. Jan M. Rabaey's group@UC Berkeley for half a year, see http://sist.shanghaitech.edu.cn/NewsDetail.asp?id=353, and are sending one student to visit Prof. Sachin Sapatnekar's group@Univ. of Minnesota in August 2017 for one year. 

3) It is easy for our members to get an intern or full-time position in the companies around the campus. See http://sist.shanghaitech.edu.cn/faculty/zhoupq/people.students.html.  


  • Figure 1. Power delivery system with multiple power domains.
  • Figure 2. Simulations results of different nominal VDDs.
  • Figure 3. Optical NoC for 3D chip [IBM].
  • Figure 4. A homogeneous multicore chip with connecting routers.
  • Figure 5. A heterogenous multicore chip, with CPU and GPU cores.
  • Figure 6. The Smart Grid [IHorizon Energy Research, United Kindom].
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