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VLSI Implementation of Fixed-coefficient Digital FIR Filters
Date:2017/4/9     Browse:250
Speaker:  Xin Lou
Time:        Apr 14, 3:00 pm – 4:00pm.
Location: Room 1A-200, SIST Building
Abstract:
Digital finite impulse response (FIR) filter is one of the most important building blocks in many digital signal processing (DSP) circuits and systems. For very large scale integration (VLSI) implementation of fixed-coefficient FIR filters, the resource-hungry multipliers can be realized by a multiple constant multiplication (MCM) block using shift and add/subsract operations. The products generated by the MCM block are then denlay and accumulated using the product accumulation block (PAB). In this talk, the efficient VLSI implementation of FIR filters will be discussed.
Bio:
Dr. Lou obtained his bachelor’s degree in Electronic Science and Technology from Zhejiang University (ZJU), China, in 2010 and Master’s degree in System-on-Chip Design from Royal Institute of Technology (KTH), Sweden, in 2012 and PhD degree in Electrical and Electronic Engineering from Nanyang Technological University (NTU), Singapore, in 2016. Then he joined VIRTUS, IC Design Centre of Excellence in the same university as a research scientist. In Mar. 2017, Dr. Lou joined School of Information Science and Technology, ShanghaiTech University as an assistant professor. 
                                                                                                                                 SIST-Seminar17007