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EDA软件列表
Date:2017/10/25     Browse:738


Mentor:

Product Name

Part Number

Description

DESIGN,ENTRY & SYNTHESIS

 

 

HDL Designer Ap SW

207964

FPGA/ASIC中设计生成和RTL复用管理环境

Visual IP-XACT Ap SW

242631

RTL代码中创建可复用的IP-XACT标准模型

Precision RTL Synthesis Ap SW

211639

适用FPGA发展的新一代RTL综合器

Precision RTL Plus Ap SW

233858

增强型FPGA综合器

 

 

 

High-Level Design

 

 

Vista Architect Stn SW

236144

系统建模,集成,调试及架构分析

Visual SLD Pro Stn SW-MD

239656

RTL建模,集成工具

Visual SLD Pro LNL Plus Stn SW

239154

RTL建模,集成及代码检查工具

Vista HCE Op SW

239732

 

ReqTracer Ap SW

235983

需求追踪分析,管理

 

 

 

FUNCTIONAL VERIFICATION

 

 

Questa AFV Ap SW

224747

功能验证和仿真

Questa Ultra Bnd SW

248475

功能验证和仿真工具包

(includes ModelSim SE functionality)

 

(包括ModelSim SE的功能)

Quesa Codelink Runtime Ap SW

241222

软硬件协同验证仿真器

Questa Codelink Debugger Op SW

241221

软硬件协同验证调试器

Questa CDC Ap SW

243168

跨时钟域验证工具

Questa CDC-FX Op SW

222972

跨时钟域验证动态插入

Questa Formal Ap SW

243169

基于断言的形式验证工具

Questa Verification IP Library Ap SW

235831

验证IP

Questa Codelink Turbo Ap SW

241818

软硬件协同验证工具

Freescale Family Op SW

228131

freescale包(软+I38硬件协同验证)

FormalPro V8 Ap SW

204610

等效性检查工具

Schematic Generator V8 Ap SW

54769

原理图产生器


Cadence:

Item

Product Number

Description

Cadence大学计划-Custom Integrated Circuits Bundle

1

206

Virtuoso(R) Simulation Environment

2

70000

Virtuoso(R) AMS Designer Environment

3

95210

Virtuoso(R) Analog Designer Environment- XL

4

95510

Virtuoso(R) Implementation Aware Design Option

5

70040

Virtuoso(R) Behavioral Modeling Optiong

6

70050

Virtuoso(R) SMG Runtime-10 Pack

7

900

Cadence(R) SKILL Development Environment

8

21060

Virtuoso(R) Schematic VHDL Interface

9

21400

Virtuoso(R) Schematic Editor Verilog(R) Interface

10

95115

Virtuoso(R) Schematic Editor XL

11

32100

Virtuoso(R) Analog Oasis Run-Time Option

12

95310

Virtuoso(R) Layout Suite XL

13

3300

Virtuoso(R) Chip Assembly Router

14

276

Virtuoso(R) Schematic Editor HSPICE Interface

15

32760

Virtuoso(R) Analog HSPICE Interface Option

16

91400

Virtuoso(R) Multi-mode Simulation Power Option

17

91500

Virtuoso(R) Multi-mode Simulation CPU Accelerator Option

18

33580

Virtuoso(R) RelXpert

19

90004

Virtuoso(R) Multi-mode Simulation with Spectre XPS

20

91600

Spectre Extensive Partitioned Simulator

21

3500

Spectre Characterization Simulator Option

22

940

Virtuoso(R) EDIF 200 Reader

23

945

Virtuoso(R) EDIF 200 Writer

24

12141

Cadence(R) Design Framework Integrator's Toolkit

25

365

Dracula(R) Graphical User Interface

26

70520

Dracula(R) Physical Verification and Extraction Suite

27

71520

Diva(R) Physical Verification and Extraction Suite

28

72110

Assura(TM) Design Rule Checker

29

72120

Assura(TM) Layout Vs. Schematic Verifier

30

72140

Assura(TM) Graphical User Interface Option

31

72150

Assura(TM) Multiprocessor Option

32

QRCX300

Cadence(R) QRC Extraction - XL

33

K2200

Cadence(R) QuickView Layout and Mask Data Vierer

34

K2211

Cadence(R) QuickView Sing-off Data Analysis Environment

35

95311

Virtuoso(R) DFM Option

36

96210

Cadence(R) Physical Verification System Design Rule Checker XL

37

96220

Cadence(R) Physical Verification System Layout vs. Schematic Checker XL

38

96240

Cadence(R) Physical Verification System Results Manager

39

96246

Cadence(R) Physical Verification System QuickView Signoff Environment

40

96300

Cadence(R) Physical Verification System Constraint Validator

41

96330

Cadence(R) Physical Verification System Advanced Device Option

42

96320

Cadence(R) Physical Verification System Advanced Analysis Option

43

96340

Cadence(R) Physical Verification System Pattern Matching Option

44

96350

Cadence(R) Physical Verification System Mask Rule Check Option

45

96400

Virtuoso(R) Integrated Physical Verification System Option for Layout Suite

Cadence大学计划软件-Digital Integrated Circuits Bundle

1

VPS200

Virtuoso(R) Power System-XL

2

VTS200

Voltus IC Power Integrity Solution-XL

3

FE725

Encounter(TM) Timing System-XL

4

FE830

ETS Advanced Analysis GXL Option

5

EDS200

Encounter(TM) Digital Implementation System XL

6

EDS10

Encounter(TM) Low Power GXL Option

7

EDS20

Encounter(TM) Mixed Signal GXL Option

8

ET021

Architect Advanced Option to RC

9

ET023

Encounter True Time Test Advanced

10

ET010

Encounter Diagnostics Basic

11

CFM200

Encounter(TM) Conformal - XL

12

CFM500

Encounter(TM) Conformal Low Power - XL

13

RC200

Encounter(TM) RTL Compiler - XL

14

RC310

Encounter(TM) RTL Compiler Low Power Option

15

RC340

Encounter(TM) RTL Compiler Advanced Physical Option


Synopsys:

Asia Pac BackEnd University Bundle

Product Code

Product Description

Description

Prerequisite Notes

2673-0

Library Compiler

Prepares libraries from Open-Source Liberty format with timing, area, power, test and function information for use in Galaxy Flow (DC family, PT family, ICC).

 

3297-0

IC WorkBench Edit/View Plus

Fast layout viewer and editor, supporting GDSII and OASIS formats.

Internal Comments: ICWBEV+ is required for large-area GDSII/OASIS database viewing within Sentaurus TCAD, Sentaurus Lithography, and ICV.

3335-0

VCS MX

Verilog, VHDL, SystemVerilog and SystemC simulator with native testbench, plus support for VMM/UVM/OVM methodologies and Discovery VIP. Includes built-in debugger for design, testbench, assertions, and coverage visualization.

 

4204-0

ESP-CV

ESP-CV performs Verilog vs. SPICE netlist equivalence checking for functional verification of full-custom memories, datapath blocks and IO cells.

 

4270-0

IC Compiler

Single convergent netlist to post route solution for 28nm and older technologies. Takes as input gate level netlist, detailed floorplan, timing constraints, physical and timing libraries, and foundry process data and generates GDSII output.

 

4278-0

PrimeRail

Advanced gate-level IR-drop and electromigration analysis tool; includes static and dynamic full-chip analysis capability.

Internal Comments: Companion product for IC Compiler based flows

4295-0

NanoTime

Next generation transistor-level static timing analysis solution for custom design.

 

4311-0

CustomSim CircuitCheck op.

Static and dynamic functions for parametric checks, ERC, logic & timing diagnostics, signal integrity and leakage checks.

Prerequisites: CustomSim (4944-0) or CustomSim-MS (4299-0) or CustomSim-SC (4298-0)

4313-0

CustomSim Digital Co-Sim op.

Enables Co-Simulation with VCS and 3rd Party Digital Simulators

Prerequisites: CustomSim (4944-0) or CustomSim-MS (4299-0) or CustomSim-SC (4298-0)

4320-0

IC Compiler MR 8:8 Node Dist Rt. Op

Add-on to IC Compiler (4270-0), IC Compiler-XP(3348-0), and IC Compiler-PC (4271-0) for distributed routing for any number of nodes with the classic router. Not required or supported with Zroute. Zroute is the default router in ICC, ICC-PC and ICC-DP

Prerequisites: IC Compiler (4270-0) or IC Compiler-PC (4271-0) or IC Compiler-XP (3348-0)

4463-0

PrimeTime PX Add-On

Gate-level power analysis option; includes average power, peak power and cycle-based power analysis. Support for vector-free and simulation-based stimulus for analysis.

Prerequisites: PrimeTime (2595-0) or PrimeTime SI (3222-0). For optional waveform viewing, several alternatives are available. Sell Synopsys Products 5005-0 CosmosScope or 4644-0 Custom WaveView. Another alternative is to OEM nWave (2530-0).

4464-0

NanoTime Ultra Add-On

Provides advanced technologies, such as SI.

Prerequisites: NanoTime (4295-0)

4645-0

Analysis Command Environment

Tcl and Perl-driven high-level functional APIs for application-specific customization.

Custom WaveView (4644-0) or CustomExplorer (4643-0)

4646-0

SX-CDS Link

SX-CDS Link framework integrations offer direct schematic-to-viewer cross probing capabilities from Cadence Design Systems Virtuoso Platform products.

Custom WaveView (4644-0) or CustomExplorer (4643-0)

4647-0

SX-DAIC Link

SX-DAIC Link framework integrations offer direct schematic-to-viewer cross probing capabilities from Mentor Graphics Design Architect.

Custom WaveView (4644-0) or CustomExplorer (4643-0)

4648-0

SX-ADP Link

SX-ADP Link framework integrations offer direct schematic-to-viewer cross probing capabilities from Silicon Canvas ADP.

Custom WaveView (4644-0) or CustomExplorer (4643-0)

4649-0

SX-JEDAT Link

SX-JEDAT Link framework integrations offer direct schematic-to-viewer cross probing capabilities from JEDAT SX.

Custom WaveView (4644-0) or CustomExplorer (4643-0)

4650-0

SX-CDS ENS

SX-CDS ENS Link framework integrations offer direct extracted netlist-to-viewer cross probing capabilities from Cadence Design Systems Virtuoso Platform products.

Custom WaveView (4644-0) or CustomExplorer (4643-0)

4652-0

SX-DATA options

WaveView Analyzer / Spice Explorer support for oscilloscope waveform data analysis.

Custom WaveView (4644-0) or CustomExplorer (4643-0)

4660-0

HSPICE

High accuracy analog circuit simulator.

 

4662-0

IC Compiler Design Planning

Hierarchical design planning for feasibility analysis and detailed floorplanning and is fully integrated with IC Compiler.

 

4756-0

CustomExplorer Ultra

Netlist-based mixed-signal verification and debug environment.

 

4942-0

Custom Designer SE

Next-Generation Custom Schematic Editor

 

4943-0

Custom Designer LE

Next-Generation Custom Layout Editor

 

4944-0

CustomSim

Shared license fastspice product for XA, HSIM and NanoSim

 

5005-0

CosmosScope

Waveform viewer and postprocessing for analog and mixed-signal waveforms. Supports HSPICE, Nanosim, VCS and Saber.

 

6745-0

IC Validator/Hercules DP

Enables the customer to use one additional CPU for any multi-processing task with Hercules or IC Validator

Prerequisites: IC Validator/Hercules (6746-0), or IC Validator/Hercules LVS (4277-0), or IC Validator/Hercules DRC (6747-0)

6746-0

IC Validator/Hercules

This is equivalent to a combination of IC Validator/Hercules LVS (4277-0), plus IC Validator/Hercules DRC (6747-0), plus one IC Validator/Hercules DP (6745-0). It allows a DRC and an LVS job to run concurrently. Either job can use the DP license.

We recommend you also sell a copy of IC WorkBench Edit/View Plus (3297-0) with this license. Free upgrades from: 5183-0 Hercules HDRC (1998.2+) +5191-0 Hercules HLVS (1998.2+) -OR- 5184-0 Hercules HDRC w/Herc Basic + 5182-0 Hercules HLVS w/Herc Basic

6918-0

Custom Designer LE Plus Add-On

Custom Designer SDL significantly improves layout productivity be managing the complex job of synchronizing the schematic of a design and its layout.

4943-0 Custom Designer LE

7584-0

StarRC Ultra

Parasitic Extraction for advanced gate-level and transistor-level design and analysis, including 20nm DPT with multi-value SPEF support, FinFET, 3D-IC, multi-corner and statistical signoff extraction.

Prerequisites: Galaxy-3D (9936-0) Internal Comments: Prerequisite required by StarRC Ultra 3D-IC feature

2593-0

Formality

Fast, easy to use RTL-gate and gate-gate equivalence checking for DC Ultra/DC Grapical. Incudes low power support and multi-core.

Internal Comments: Combined with DC Ultra/DC Graphical, provides the highest QoR that is verifiable. Differentiators include: completion with DCU, all power state verification, ease of use and integration with DC flow. Can use up to 4 cores/license

A291-0

FineSim spice2

FineSim is a high-performance accelerated SPICE simulator. FineSim's unique multi-core/multi-machine simulation capability allows users to drastically improve simulation performance and capacity. FineSim is well-suited for simulation of large, complex analog circuits, as well as DRAM/SRAM/Flash memory design. FineSim, in combination with its simulation environment, provides an accelerated SPICE simulation solution that boosts productivity.

 

A637-0

VCS AMS

mixed-signal verification solution, incorporating VCS functional verification with CustomSim FastSPICE simulator and its simulation environment, delivers advanced functional and low-power verification technologies combined with industry-best performance and capacity for faster mixed-signal SoC regression testing.

 

9342-0

IC Compiler Custom Co-Design

Full featured custom layout editor including interactive routing integrated with IC Compiler.

 

9343-0

Galaxy Custom Router

Auto custom router

Any one of following, 9342-0 IC Compiler Custom Co-Design B184-01 Maxwell Advanced

9981-0

Custom Designer SE Plus Add-On

Advanced features for Custom Designer SE, for instance multiple testbench

4942-0

A011-0

nAnalyzer

Clock tree extraction and analysis, timing report (primetime) support

Verdi

A013-0

nECO

Graphical ECO editor

Either Verdi, Debussy, or (nTrace+nSchema) is a pre-requisite.

A015-0

nLint

Design linting (in maintenance mode)

None

A034-0

Siloti

Visibility enhancement automation

None

A039-0

Verdi-3

Verdi-3 debug automation

None (use same license key as Verdi)

A038-0

Verdi - Power Aware Debug

Power aware debug

Verdi

A041-0

Laker ADP

Laker Advanced Design Platform (ADP) includes schematic editing, simulation environment and waveform display capabilties for custom IC design

 

A042-0

Laker SE

Laker SE is the schematic editing component of Laker Advanced Design Platform

 

A043-0

Laker Custom Row Placer

Laker Custom Row Placer automates the creation of custom digital blocks by adding row-based placement capability for users of Laker L3 or Laker L4

Laker_L3 or Laker_L4 (A056-0 or A058-0)

A044-0

Laker Custom Digital Router

Laker Custom Digital Router adds automatic routing for custom digital circuits for users of Laker L3 or Laker L4

Laker_L3 or Laker_L4 (A056-0 or A058-0)

A049-0

Laker FPD Editor

Laker FPD Editor is a unified environment for creating, editing, equal resistance routing and gateway model realization for flat panel layout

 

A050-0

Laker FPD L2 - Adv Flat Panel

Laker FPD L2 provides advanced layout functionality such as schematic-driven layout, job file generator, mask shot planning and exposure analysis for flat panel layout

 

A052-0

Laker Blitz - Chip Layout Editor

Laker Blitz chip level editor provides very high speed reading, writing and merging of GDSII design data along with all of Laker L1 editing features

 

A053-0

Laker L0 - Viewer

Laker L0 provides basic layout viewing capability

 

A054-0

Laker L1 - Basic Custom Layout

Laker L1 provides basic layout editing capability

 

A055-0

Laker L2 - Std Custom Layout

Laker L2 includes all Laker L1 features and adds additional layout editing capability such as rule-driven layout and built-in magic cells device generators

 

A056-0

Laker L3 - Adv Custom Layout

Laker L3 includes all Laker L2 features and adds advanced editing features such as schematic-driven layout editing, the matched device creator (MDC) and the stick diagram creator (SDC)

 

A058-0

Laker L4 - Analog Prototyping

Laker L4 includes all Laker L3 features and adds automatic constraint extraction and placement of analog designs

 

A060-0

Laker Advanced Geometry Add-on

Laker liveDRC extends the rule-driven layout capabilities of Laker L3 to support design rules used in 28nm and below process geometries

Laker_L3(A056-0)




Asia Pac FrontEnd University Bundle

Product Code

Product Description

Description

Prerequisite Notes

2572-0

TetraMAX IddQ Test

Verifies IDDQ compliance for TetraMAX ATPG and functional vectors.

Prerequisites: VCS (3335-0) or IEEE-compliant Verilog simulator

2574-0

TetraMAX DSMTest

Enables DSM fault models: transition, path delay, bridging and dynamic bridging. Also enables power-aware and timing-aware features.

Prerequisites: TetraMAX ATPG (2588-0)

2588-0

TetraMAX ATPG

Provides manufacturing test patterns for scan designs. Includes failure diagnostics for defect isolation, and fault simulation for functional vectors. Does not provide DFT synthesis.

Prerequisites: DFTMAX (4280-0) for adaptive scan. No prerequisite for standard scan.

2599-0

Pioneer NTB with Vera

Standalone SystemVerilog and OpenVera testbench automation tool. It allows users to create SystemVerilog or OpenVera testbench that can be run with VCS and 3rd party simulators. Developer Kit includes compilation, runtime and debug.

 

2618-0

coreBuilder

Guides the IP designer through the process of capturing the necessary design files, information and designer knowledge necessary to deliver high quality, easily reusable cores supporting IP-XACT.

 

2663-0

DC Ultra

RTL Synthesis solution for all designs. Delivers best-in-class timing, area and power results. Includes Topographical Technology to boost productivity.

Prerequisites: (HDL Compiler Verilog (2671-0) and DesignWare Library (2925-0)) or (VHDL Compiler (2681-0) and DesignWare Library (2925-0)) Internal Comments: Sell as standard synthesis seat for the most comprehensive synthesis solution. Also sell as a com

2671-0

HDL Compiler Verilog

Front-end for Design Compiler, Reads in Verilog or SystemVerilog HDL description.

Prerequisites: DC Expert (2661-0) or DC Ultra (2663-0)

2673-0

Library Compiler

Prepares libraries from Open-Source Liberty format with timing, area, power, test and function information for use in Galaxy Flow (DC family, PT family, ICC).

 

2678-0

Power Compiler

Complete power synthesis and optimization solution. Provides optimization for multi-voltage, multi-Vt, advanced clock-gating and power management cell insertion via UPF. Enables UPF for DC Ultra.

Prerequisites: DC Expert (2661-0) or DC Ultra (2663-0) for power optimization. Internal Comments: Power Compiler is a requirement for UPF usage in DC Ultra.

2681-0

VHDL Compiler

Front-end for Design Compiler, Reads in VHDL description.

Prerequisites: DC Expert (2661-0) or DC Ultra (2663-0)

2925-0

DesignWare Library

Includes key infrastructure IP for SoC design & verification datapath, building block IP, Foundry Libraries, AMBA OCB, Peripherals ( DMA, UART, I2C#), Microcontrollers (8051, 6811), Memory IP & Verification IP. 9/7/2004

 

2926-0

DesignWare Developer

Tool for Generation of User Defined DesignWare components.

 

3160-0

Design Vision

Graphical User Interface(GUI) for Design Compiler, enables intuitive and easy visual analysis of designs.

Prerequisites: DC Expert (2661-0) or DC Ultra (2663-0) Internal Comments: Needed for Design Compiler Graphical

3335-0

VCS MX

Verilog, VHDL, SystemVerilog and SystemC simulator with native testbench, plus support for VMM/UVM/OVM methodologies and Discovery VIP. Includes built-in debugger for design, testbench, assertions, and coverage visualization.

 

3353-0

CoreAssembler

Tool for generating connectivity netlists for Subsyystems, full Soc as well as test benches supporting SystemVeriliog Methodolgies

 

3834-0

MVSIM

MVSIM provides comprehensive verification coverage for low-power designs using advanced power management techniques. MVSIM enables accurate RTL or gate-level Voltage-Aware simulation natively in VCS (PLI mode continues to be available).

 

4204-0

ESP-CV

ESP-CV performs Verilog vs. SPICE netlist equivalence checking for functional verification of full-custom memories, datapath blocks and IO cells.

 

4280-0

DFTMAX

Provides compression, scan, and boundary synthesis. Also enables TetraMAX ATPG (2588-0) for compression.

Prerequisites: DC Expert (2661-0) or DC Ultra (2663-0).

4295-0

NanoTime

Next generation transistor-level static timing analysis solution for custom design.

 

4463-0

PrimeTime PX Add-On

Gate-level power analysis option; includes average power, peak power and cycle-based power analysis. Support for vector-free and simulation-based stimulus for analysis.

Prerequisites: PrimeTime (2595-0) or PrimeTime SI (3222-0). For optional waveform viewing, several alternatives are available. Sell Synopsys Products 5005-0 CosmosScope or 4644-0 Custom WaveView. Another alternative is to OEM nWave (2530-0).

4464-0

NanoTime Ultra Add-On

Provides advanced technologies, such as SI.

Prerequisites: NanoTime (4295-0)

4756-0

CustomExplorer Ultra

Netlist-based mixed-signal verification and debug environment.

 

9141-0

DesignWare TLM Library

Licenses to run TLM models respresenting specific Synopsys DesignWare interface IP

 

A035-0

Siloti-correlation

RTL and Gate level design correlation

Siloti

A036-0

Siloti-Relay

Simulation replay based on FSDB

Siloti

4770-0

PrimeTime ADV

Advanced gate-level static timing analysis (STA) and signoff tool, including advanced ECO, latch analysis and Sigma-based On-chip-variation handling

 

6585-0

VC LP 2014

Advanced low power static checking solution