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Prof. Xin Lou / 娄鑫 助理教授、研究员

Tel:  (021) 20685375
Email: louxin@@shanghaitech.edu.cn
Office: Room 1D-301E, SIST Building, No.393 Huaxia Middle Road, Pudong Area Shanghai
Major: EE
Website:
Xin Lou Research Group Recruitment (Click Here)

RESEARCH INTERESTS

  • Digital FIR filter design and implementation
  • Energy-efficient VLSI digital signal processing circuits and systems 
  • VLSI cryptographic circuits and systems

BIOGRAPHY

Dr. Lou obtained his bachelor’s degree in Electronic Science and Technology from Zhejiang University (ZJU), China, in 2010 and Master’s degree in System-on-Chip Design from Royal Institute of Technology (KTH), Sweden, in 2012 and PhD degree in Electrical and Electronic Engineering from Nanyang Technological University (NTU), Singapore, in 2016. Then he joined VIRTUS, IC Design Centre of Excellence in the same university as a research scientist. In Feb. 2017, Dr. Lou joined School of Information Science and Technology, ShanghaiTech University as an assistant professor, PI.

SELECTED PUBLICATIONS

1. X. Lou*, Y. J. Yu and P. K. Meher, “Fine-Grained Critical Path Analysis and Optimization for Area-Time Efficient Realization of Multiple Constant Multiplications”, IEEE Transactions on Circuits and Systems I, vol 62, no. 3, pp. 863-872, Mar. 2015.

2. X. Lou*, Y. J. Yu and P. K. Meher, “New Approach to the Reduction of Sign-extension Overhead for Efficient Implementation of Multiple Constant Multiplications”, IEEE Transactions on Circuits and Systems I, vol 62, no. 11, pp. 2695-2705, Nov. 2015.

3. X. Lou*, Y. J. Yu and P. K. Meher, “Analysis and Optimization of Product-Accumulation Section for Efficient Implementation of FIR Filters”, IEEE Transactions on Circuits and Systems I, vol 63, no. 10, pp. 1701-1713, Oct. 2016.

4. X. Lou*, Y. J. Yu and P. K. Meher, “Lower Bound Analysis and Perturbation of Critical Path for Area-Time Efficient Multiple Constant Multiplications”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol 36, no. 2, pp. 313-324, Feb. 2017.

5. P. K. Meher, and X. Lou*, “Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for GF(2^m) Based on Irreducible All-One Polynomials”, IEEE Transactions on Circuits and Systems I, vol 64, no. 2, pp. 313-324, Feb. 2017.

6. X. Lou*, P. K. Meher, Y. J. Yu and W. B. Ye, “Novel Structure for Area-Energy-Efficient Implementation of FIR Filter”, IEEE Transactions on Circuits and Systems II, in press.