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VLSI Layout Hotspot Detection: From Feature Optimization, Online Learning, to Deep Learning
Date: 2017/3/10             Browse: 140
Seminar Topic: VLSI Layout Hotspot Detection: From Feature Optimization,  Online Learning, to Deep Learning

Speaker: Bei Yu
Time: Mar. 15, 10:00 a.m. - 11:00 a.m.
Venue:  Room 1A-200, SIST Building


The continuous shrinking of feature sizes for very large scale integrated (VLSI) circuits with advanced lithography has been a holy grail for the semiconductor industry to achieve ever-higher device density and performance with reduced cost per transistor. However, the aggressive scaling has been facing severe challenges due to lithography variations. In this talk, I will introduce our recent series of works on lithography hotspot detection, where feature optimization, online learning, as well as deep learning techniques are developed. At the end of this talk, I will also briefly introduce HK PhD fellowship summer workshop 2017.


Prof. Yu received his Ph.D. degree from the Department of Electrical and Computer Engineering, University of Texas at Austin in 2014. He is currently an Assistant Professor in the Department of Computer Science and Engineering, The Chinese University of Hong Kong.

He has served in the editorial boards of Integration, the VLSI Journal and IET Cyber-Physical Systems: Theory & Applications. He has received three Best Paper Awards at SPIE Advanced Lithography Conference 2016, ICCAD 2013, and ASPDAC 2012, four other Best Paper Award Nominations at ISPD 2017, DAC 2014, ASPDAC 2013, ICCAD 2011, and three ICCAD contest awards in 2015, 2013 and 2012. He has also received EDAA Outstanding Dissertation Award in 2014, Chinese Government Award for Outstanding Students Abroad in 2014, SPIE Scholarship in 2013, and IBM PhD Scholarship in 2012.

Seminar 17003