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A Statistical Methodology for Noise Sensor Placement and Full-Chip Voltage Map Generation
Date: 2016/4/26             Browse: 208

Xiaochen Liu, Shupeng Sun, Pingqiang Zhou, Xin Li and Haifeng Qian, "A Statistical Methodology for Noise Sensor Placement and Full-Chip Voltage Map Generation," Proceedings of the ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 1-6, June 2015.


Abstract:  Noise margin violation, also known as voltage emergency induced by continuously reducing noise margin and increasing magnitude of current swings, is becoming a severe threat to the correct execution of applications in processors. Noise sensors can be placed in the non-function area of processors to detect such emergencies by monitoring runtime voltage fluctuations. In this work, we aim to accurately predict the voltage droops using a small set of sensors. We achieve our goal in two steps: We first propose a methodology via group lasso approach to select the optimal set of noise sensors, then build a practical model via ordinary least-squares fitting approach to predict the voltage in the function area of the chip, using the selected sensors in non-function area. Experiment results show that when compared to the full-chip voltage transient simulation, the prediction error of our model is much less than 0.01, and compared to prior work, our approach can achieve better error rates of voltage emergency detection (less than half).

About the conference DAC (

The Design Automation Conference (DAC) is recognized as the flagship conference for design and automation of electronic systems. It is sponsored by the Association for Computing Machinery (ACM), the Electronic Design Automation Consortium (EDA Consortium), and the Institute of Electrical and Electronics Engineers (IEEE), and is supported by ACM's Special Interest Group on Design Automation (SIGDA).