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A System Perspective of Power Delivery at Sub-22nm: Modeling, Impact and Solution
Date: 2016/3/29             Browse: 491

A System Perspective of Power Delivery at Sub-22nm: Modeling, Impact and Solution

Speaker: Cheng Zhuo

Time: Mar 29, 10:30am - 11:30am.

Location: Room 310, Teaching Building


Power delivery has always been the key to the success of a chip. However, at sub-22nm, design of power delivery has been more challenging than ever. On one hand, the noise margin has been shrinking to tens of mV due to the scaling of supply level and data rate, thereby enforcing a more robust power delivery design. On the other hand, SoC market demands set a strict constraint on BOM cost and limit on-chip and on-package resources for power delivery. Thus, in order to provide a desired power delivery solution, it is crucial than ever to understand three fundamental questions: (1) What is in the power delivery system? (2) Why is it important? (3) How to optimize? Unlike traditional power delivery works focusing on back-end details, this presentation tackles the issue from the system perspective.  It first addresses the challenges and issues in sub-22nm power delivery design. Then it discusses in details with silicon data about power delivery modeling. After that the presentation covers the impact of power delivery on the system. Finally, it provides a cross-layer approach for power delivery and architecture co-exploration.


Dr. Cheng Zhuo received B.S. and M.S degrees from Zhejiang University, in 2005 and 2007 respectively. He received Ph.D degree in Computer Science & Engineering in 2010 from University of Michigan, Ann Abror. After graduation he joined Intel Corp., USA, in 2011. Before leaving Intel in 2016, he was Staff R&D leading multiple research areas for sub-14nm technologies. Dr. Zhuo joined Department of Information Science & Electronic Engineering of Zhejiang University in 2016 and was selected to “National 1000 Talented Young Scholar Program". His current research interests include 3D IC design, power & signal integrity, application specific accelerator design, low power sensor design, and general VLSI EDA areas.

Dr. Zhuo has been invited to many technical program committees of top conferences in VLSI and EDA domains, including DAC, ICCAD, ASPDAC, etc.. He has published over 40 papers, and 1 book chapter. He has received 4 Intel Division Recognition awards, 2012 ACM SIGDA technical leadership award and Best Paper Nomination in DAC 2016. He is a senior member of IEEE.


SIST-Seminar 16022