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The coming age of digital implementation flow for modern chip designs
Date: 2015/7/7             Browse: 386

Speaker: Zhuo Li

Time: July 7th, 2:00-3:00pm

Location: Room 220, Building 8, Yueyang Road Campus


EDA (Electronic Design Automation) tools enable circuit designers to design complicated circuits and chips with speed as high as 5G Hz and power as low as several milliwatts, consisting of millions to billions of transistors on a small die. These chips are hearts of most electronic devices seen in our daily life, such as cell phones, tablets, computers, network and communication chips, game boxes, and high performance servers. Modern computer and semiconductor industry cannot survive without EDA tools.

As the manufacturing cost continues to increase in the advanced technology nodes beyond 20 nm, there exits more demanding requirement for area and power efficient devices. Therefore, designers have to pack more and more logic functionalities into a small-sized die to balance the fabrication cost and chip power. Naturally, it becomes increasingly challenging to achieve design closure on these enormous chips with tight performance and power constraints. Traditional digital implementation flow needs to revitalize itself to handle more constraints than ever, such as congestion and timing inside placement, optimization with multiple layers of metal, hierarchical design styles and more embedded IPs, complicated logic structures, complicated design and manufacturing rules, aggressive power budgets, .etc. The next generation synthesis and implementation flow need to attack all of these problems, while still achieving faster turn-around-time at the same time to meet the short time-to-market. We need more innovations!

This talk will briefly overview the EDA field, and discuss latest problems and challenges in physical implementation flow related to placement, buffering, layer assignment, congestion mitigation, logic synthesis, clocking, routing, as well as some previous published research results and latest solutions from Industry. If time permits, the speaker will also discuss Contest in EDA area and introduce Design Automation Conference to the audience, which is recognized as the premier conference for design and automation of electronic systems.


Zhuo Li received the B.S. and M.S. degree in electrical engineering from Xi'an Jiaotong University, in 1998 and 2001, respectively, and the Ph.D. degree in computer engineering from Texas A&M University, College Station, in 2005. After graduation, he co-founded Pextra Corp, which was a startup specializing in parasitic extraction and acquired by Mentor Graphics Corp. in 2009. From 2006 to 2014, he was a Research Staff Member at IBM T.J. Watson Research Center and Austin Research Lab. He has received five IBM Outstanding Technical Achievement Awards, one IBM Outstanding Contributor Award, and 4 IBM Research O-level accomplishment awards. Currently Dr. Li is a Software Architect at Cadence Design Systems developing next generation digital implementation flow product Innovus and synthesis product Genus.


Dr. Li has issued 47 patents. He has published over 70 conference and journal papers, and has received the Best Paper Award at ASPDAC 2007, the IEEE Circuits and System Society Outstanding Young Author Award at DAC 2007, three Best Paper Award Nominations at ISPD, ICCAD and ISQED, and two Best Paper Award Nominations from IEEE TCAD. He has been serving as TPC sub-committee Chair or committee members for all major conferences in EDA area, such as DAC, ICCAD and DATE, and has received many IEEE/ACM service awards including ACM Technical Leadership Award from ACM SIGDA, SRC Mahboob Khan Outstanding Industry Liaison/Associate Award, DAC Service Award, IEEE Region 5 Outstanding Individual Member Achievement Award (twice). In 2013, as the first winner from the industry, he received IEEE CEDA Early Career Award, the top award for young researchers in EDA area. He is an Associate Editor of IEEE Transactions of Computer-Aided Design, and on Executive Committee of Design Automation Conference (DAC) as Designer Track Co-Chair in 2016.


SIST-Seminar 15029