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Design for Manufacturability and Reliability in Extreme Scaling
Date: 2015/4/3             Browse: 836

Speaker:Dr. Bei Yu

Time: Apr. 3rd, 13:00-14:30pm

Location: Room 220, Building 8, Yueyang Road Campus


The continuous shrinking of feature sizes for very large scale integrated (VLSI) circuits with advanced lithography has been a holy grail for the semiconductor industry to achieve ever-higher device density and performance with reduced cost per transistor. However, due to the more and more serious manufacturability and reliability issues, this aggressive scaling has been facing severe challenges. Multiple patterning lithography, along with other advanced lithography techniques, e.g., extreme ultraviolet, electric beam, directed self-assembly, are promising solutions to overcome these challenges. In this talk I will introduce our coherent CAD framework to provide multiple patterning lithography manufacturing friendly design. In addition our framework, consisting of layout decomposition and physical synthesis, is generic to handle other advanced lithography techniques. Besides, I will describe our physical verification tool to detect the hotspots, which are lower fidelity patterns on a layout. Integrated with a set of machine learning techniques, our tool is shown to be effective to detect most of the hotspots, and thus be able to enhance the design reliability.


Bei Yu received the Ph.D. degree in 2014 from ECE Department, University of Texas at Austin, where he is currently a Post-Doctoral Scholar, working with Prof. David Z. Pan. His current research interests include design for manufacturability and optimization algorithms.

Dr. Yu was the recipient of 2014 Outstanding Dissertation Award from EDAA in category of “New directions in physical design, design for manufacturing and CAD for analog circuits and MEMS”, the Best Paper Awards at ICCAD’13 and ASPDAC’12, three other Best Paper Award Nominations at DAC’14, ASPDAC’13, and ICCAD’11, the SPIE Education Scholarship in 2013, and the IBM Ph.D. Scholarship in 2012.        


                      SIST-Seminar 15003