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Favorable Block First: A Comprehensive Cache Scheme to Accelerate Partial Stripe Recovery of Triple Disk Failure Tolerant Arrays
Date: 2017/12/13             Browse: 32

Speaker:     Associate Prof. Chentao Wu. SJTU

Time:          Dec  13.   15:00  —  16:00

Location:    Room 1A-200, SIST Building

Host:          Prof. Shu Yin

Abstract:

With the development of cloud computing, disk arrays tolerating triple disk failures (3DFTs) are receiving more attention nowadays because they can provide high data reliability with low monetary cost. However, a challenging issue in these arrays is how to efficiently reconstruct the lost data, especially for partial stripe errors (e.g., sector and chunk errors). It is one of the most significant scenarios in practice. However, existing cache strategies are not efficient for partial stripe reconstruction in 3DFTs, which is because the complex relationships among data and parities are usually ignored during the recovery process.

To address this problem, in this paper, we proposed a comprehensive cache policy called Favorable Block First (FBF), which can speed up the partial stripe reconstruction of 3DFTs. FBF investigates the relationships among parity chains via allocating various priorities of shared chunks. Thus in the recovery process, by giving higher priorities to the chunks which are shared by more parities chains, FBF can dynamically hold the significant data in buffer cache for partial stripe reconstruction. Obviously, it increases the cache hit ratio and reduces the reconstruction time. To demonstrate the effectiveness of FBF, we conduct several simulations via Disksim. The results show that, compared to typical recovery schemes by combining with classic cache policies (e.g., LRU, LFU and ARC), FBF improves hit ratio by up to 2.47× and accelerates the reconstruction process by 14.90%, respectively.

Bio:

Chentao Wu is currently an associate professor and a Ph.D. supervisor in the Department of Computer Science and Engineering at Shanghai Jiao Tong University (SJTU), Shanghai, China. He received the PhD degree in electrical and computer engineering from Virginia Commonwealth University (VCU), Richmond, United States, in 2012. Prior to that, he received the BS, MS and PhD degrees in computer science all from Huazhong University of Science and Technology (HUST), Wuhan, China, in 2004, 2006, and 2010, respectively. His research interests include computer architecture and data storage systems. He has authored and co-authored more than 40 technical articles in prestigious international conferences and journals, such as TPDS, HPCA, DSN, IPDPS, SRDS, ICPP, ICCD, Cluster, etc. He is a member of the IEEE, ACM and China Computer Federation (CCF), a member of CCF computer architecture and data storage technical committees, a member of computer architecture technical committees in Shanghai Computer Society, and a vice chair of data storage technical committees in Shanghai Computer Society.



SIST-Seminar 17065