超威半导体(AMD)2019届毕业生专场招聘会(上科大专场宣讲会)

发布者:王雪发布时间:2018-09-13浏览次数:42

宣讲会时间:2018年9月20日 17:30-20:3017:30-18:30为产品互动展示)

宣讲会地点:上科大信息学院1A-200演讲厅

重要提醒:现场安排笔试,请同学们做好相关准备



无限未来,芯动人生!超威半导体2019校园招聘

一、关于AMD

AMD(NASDAQ: AMD)公司成立于1969年,总部位于美国加利福尼亚州桑尼维尔。AMD凭借其出类拔萃的计算技术,让人们能够以自然、智能和创新的方式与他们热爱的技术互动。AMD的显卡和微处理器运行在全球不计其数的个人电脑、平板设备、游戏机、嵌入式设备和云服务器等各种设备之上,为其提供强劲计算能力。

AMD的营业机构分布在 23 个国家和 40 多个城市, 包括十多个研发机构、将近二十多家国际销售办事处。

作为全球经济发展速度最快的国家之一和 AMD全球业务板块中最大的单一市场,中国已成为 AMD全球战略的重点之一。

·     AMD大中华区具备AMD总部所有职能部门

·     AMD大中华区是AMD全球最大单一市场,为全球PC业务营收贡献超过30%

·     AMD大中华区的制胜之道:注重高增长市场,挺进商用市场,坚守消费市场



在超过四十五年的历史中,AMD引领了高性能运算、图形,以及可视化技术方面的创新,这些都是游戏、临境感平台以及数据中心的基础。每时每刻,全球数百万的消费者、500强公司,以及尖端科学研究所都依靠AMD技术来改善他们的生活、工作和娱乐。AMD全球员工致力于打造伟大的产品,努力拓宽技术的极限。

更多信息,敬请访问www.amd.com(NASDAQ:AMD)。


二、职位信息


职位

地点

专业要求

岗位职责

ASIC Design Verification Engineer

上海,北京

EE, CS, or related

Understand the ASIC design/verification flow and help   design/verification engineers to accomplish targets.

Develop infrastructure and environment for IP/SoC level design   verification.

Closely working with Design/Architecture/Verification team to develop   new verification component.

ASIC design         and verification engineer – SMU(System Management Unit)

上海

EE, CS, or related

 Be responsible for micro-architecture and RTL implementation for SMU IP   blocks

 Be responsible for synthesis/LEDA/CDC/LEC at IP level

 Work with front-end team and physical design team on timing closure

Front-End Design Engineer

上海

EE, CS, or related

    Working with guideline and   architect to define STA target, power strategy, etc.

    Develop SOC level design for   dGPU product and make functional correct

    Setup front-end netlisting and   quality check flow

    Check and drive issue solving   and quality improvement.

    Working with physical design   team on floorplan, timing closure, power design validation, etc.

    Support ASIC bring-up.

Physical Design Engineer

上海,北京

EE, CS, or related

    Work with global Front-End   design team and physical design team for large scale ASIC chip physical   implementation.

    Focus on physical design of   deep sub-micron chips including block level (full chip) floor planning, cts,   place & route, timing closure, physical verification etc.

DFT Design Engineer

上海,北京

EE, CS, or related

    Implement DFT features   including SCAN, Boundary SCAN, MBIST, Analog Macro test logic and etc.

    Generate and verify DFT   structural patterns and functional patterns.

    Generate DFT related timing   constraints and work with PD team for timing closure.

    Participate in ATE bring-up   and debug the DFT patterns on ATE.

Software Development Engineer

上海

EE, CS, SW, or related

    Work as part of the global   Software Customer Support engineering team to design and maintain the   graphics device driver and other software components

    Resolve problem reports related   to graphics device driver including troubleshooting, debugging, & defect   correction

    Specify, design, and implement   new ASIC and software features

    Coordinate closely with peers   at both Asia and North America to ensure timely and effective communication   of all assigned work activities.

    Track the issues per assigned   customer projects to make sure its in time assignment, resolution development   and fix verification.

    Represent AMD software   occasionally to be customer facing, for technical challenging issue   explanation, status communication etc.


  Graphics Driver Engineer

上海

EE, CS, SW, or related

    Design, develop and debug   kernel mode driver, ISP driver, graphics driver, including   DirectX/OpenGL/Vulkan drivers.

    Work on supporting next   generation Microsoft Windows,  Linux   and Virtualization operation system

    Work on bring up and support   AMD next generation APU/GPU

    Maintain current driver and   improve performance

    Design new rendering   technologies

    Support key OEM customers and   ISVs

System Software Engineer      

上海

EE, CS, SW, or related

    Design, develop, and debug   System Software (UEFI Firmware, BIOS, SMU) for internal/external systems and   platforms that use AMD APU/CPU, AMD chipset, and 3rd party chipsets.

    Participant in day-to-day   Firmware development work as key part of global organization using C   languages; will need to interact with internal organizations and customers.

    Assist APU/CPU validation,   platform validation, and debug engineers to develop/debug system and silicon   issues

    Provide consultation to   internal and external customers regarding AMD features and programming   requirements.

Systems Design Engineer – IPSE Engineer

上海

EE, CS, or related

    Work closely with IP design   team to define IP validation test plan for both pre-silicon (emulation) and   post-silicon

    Lead ASIC/ IP feature bring-up   and validation, ensure coverage and schedule will meet silicon tape-out date

    Drive cross-team (ASIC design,   platform, driver) collaboration to enable IP features and optimize   performance

    Lead related engineering teams   (global) to debug related issues for related IP domain

    Work with characterization   team to figure out the optimized clocks/voltages for related IP domain

Graphic Performance Verification and Analysis

上海

EE, CS, or related

    Co-Work with World Wide   Performance Verification and Design Team

    In pre-silicon:

    Learn new features, write   test plan and new tests for new graphics chips

    Debug emulate for function   error

    Debug simulate for function   error and low performance

     Continuous team and self-growth

    Innovation/patent

    Initiate and Lead Research on   GPU architect

    Write performance analysis   tools

Graphics and parallel computing software architect

上海

EE, CS, or related

    Co-Work with World Wide   Performance analysis and Design Team

    In post-silicon:

    Work with SW/HW team to   analyze the benchmark/Game performance

    Check/Optimize chip setting   for better performance

    Performance compare/analysis   with the competitors’

    Develop performance   analysis/model tools for post-silicon workflow

    Performance analysis for each   rendering algorithm in game/benchmark

    Research new GPU architecture   to improve performance

    In pre-silicon:

    Simulate rendering algorithm   on RTL model to research/analyze performance issue on new GPU architecture

    Write demo performance case   based on algorithm analysis result

Dep-Tile Synthesis Engineer

上海

EE, CS, or related

Closely Working with global IP design team and SOC   physical design team for ASIC chip synthesis

Focus on block synthesis to sign off timing and improve   synthesis netlist quality

Co-work with PD owners to improve place's QoR.

三、应聘流程:

网申投递摩尔空中宣讲进校宣讲现场笔试面试录用签约

五、招聘网站:

网申及更多信息请登录http://campus.51job.com/amd2019,AMD期待您的加入!