Leakage Power Reduction in Multicore Chips via Online Decap Modulation


Leilei Wang and Pingqiang Zhou, "Leakage Power Reduction inMulticore Chips via Online Decap Modulation," in China SemiconductorTechnology International Conference (CISTIC), March 2016.

(BestStudent Paper Nomination)


Abstract: The decap leakage constitutes a significant part oftotal leakage in multicore processors. Leaking decap is widely used in chips toprovide transient power to function blocks, and the amount of decap placed overmulticore chip is determined by the worst case at design time. Considering thatthe decaps do not have to be kept 100% “on” when the chip is running workloads, inthis paper we propose an ideal online approach to adapt the percentage of “on” capacitancein the decaps to the dynamic need of the core loads, and therefore to reducethe leakage power consumption in the chip. Our approach is based on theequivalent resistance model of the power sources (power supply pins and localdecaps) and the core loads, and a novel fast algorithm is developed todetermine the required amount of decap at runtime. Results on a set ofmulticore test cases show that our approach can achieve up to 48% saving indecap leakage.

About the conference:  CISTIC,http://www.semiconchina.org/article_1829_818.htm

CISTIC is one of the largest and the most comprehensive annualsemiconductor technology conferences in China. It is organized by SEMI and IEEE-EDS , co-organized by ICMTIA, and co-sponsored by ECS, MRS and theChina Electronics Materials Industry Association. The conference covers allaspects of semiconductor technology and manufacturing, including devices,design, lithography, integration, materials, processes, and manufacturing, aswell as emerging semiconductor technologies and silicon material applications.